What is Serial Wire Viewer (SWV) in Arm Cortex-M?
Serial Wire Viewer (SWV) is a real-time trace functionality that is available in Arm Cortex-M microcontrollers. It allows real-time data…
Arm Cortex-M DAP bus and interconnect architecture Explained
The Arm Cortex-M series of processors feature a Debug Access Port (DAP) that provides debug capability and access to the…
Controlling Clocks and PLL for Power Savings in Cortex-M3
The Cortex-M3 processor provides multiple clock control features that allow significant power savings by slowing or stopping clocks when parts…
Sleep-on-Exit for Automated Low Power in Cortex-M3 (Explained)
Sleep-on-exit is a feature in Cortex-M3 processors that allows the processor to automatically enter a low power sleep mode when…
Highlights
Latest Arm
Software debuggers and configuring for CoreSight components (Arm Cortex-M)
Debugging software on Arm Cortex-M devices requires configuring the CoreSight components like the Embedded Trace Macrocell (ETM), Trace Port Interface…
Differences between JTAG-DP and SWJ-DP debug ports (Arm Cortex-M)
The JTAG-DP and SWJ-DP are two commonly used debug ports for ARM Cortex-M series microcontrollers. Both provide debug access and…
Supported Bus Protocols in the Cortex-M System Design Kit
The Cortex-M System Design Kit supports a range of bus protocols that allow the Cortex-M processor to interface with peripheral…
Deep Sleep Mode for Maximum Power Savings in Cortex-M3
The Cortex-M3 processor offers a deep sleep mode that allows the system to enter an extremely low power state while…
Resolving ld Library and Architecture Errors when Compiling for Cortex-M4
When compiling code for the ARM Cortex-M4 processor, you may encounter linker errors related to incompatible libraries or architecture mismatches.…
ARM Cross-Compilation Tips
Cross-compiling for ARM can seem daunting at first, but with the right tools and techniques, it can be straightforward and…
Memory Map Regions and Access Behavior in Cortex-M3
The Cortex-M3 memory map is divided into several regions, each with specific access behaviors. The Code region stores program instructions…
Cortex-M3 Memory Region Shareability and Cache Policies (Explained)
The Cortex-M3 memory system allows configuring memory regions to be shareable or non-shareable between processors. It also allows configuring cache…
What is the difference between ARM Cortex-A55 and A76?
The ARM Cortex-A55 and Cortex-A76 are two of ARM's most popular CPU cores used in mobile devices. The Cortex-A55 is…
