The Arm Cortex-M series of processors feature a Debug Access Port (DAP) that provides debug capability and access to the processor’s internal state while it is running. The DAP uses a standard JTAG interface and allows debugging tools like GDB to halt, single-step, and examine registers and memory on the target device. This article will provide an in-depth explanation of the Cortex-M DAP bus and interconnect architecture and how it enables effective debugging.
Overview of Cortex-M DAP
The Cortex-M DAP consists of two main components:
- DAP controller – implements the DAP protocol and interfaces with the processor
- DAP router – provides routing between the DAP controller and APB interfaces
The DAP controller is the main interface for debug tools to access the internal state of the processor and peripherals. It communicates with the external debugger via a JTAG interface. The DAP router routes these debug requests between the DAP controller and APB interfaces to access memory mapped resources.
Key Features of Cortex-M DAP
- Up to 16 breakpoints and 6 watchpoints
- Unlimited hardware and software breakpoints
- ROM table programming for debug authentication
- Access port protection unit
- Cross-trigger interface for linking and synchronizing events
These capabilities allow the DAP to control and monitor program execution, access memory and peripherals, and integrate with other system components for advanced debugging.
Cortex-M DAP Controller
The DAP controller is the main interface between the external debug probe and the internal resources of the Cortex-M processor. It implements the Arm Debug Interface Architecture (DIA) protocol and JTAG interface for communication with the debugger. The key functions of the DAP controller include:
- JTAG and SWD host interface – Supports JTAG or SWD for connection to external debugger
- DIA packet processing – Decodes DIA requests from debugger and initiates operations
- Breakpoint and watchpoint controls – Manages hardware breakpoints and watchpoints
- System memory access – Provides debugger access to memory mapped resources
- System registers access – Allows debugger read/write access to system registers
- Cross-triggering – Synchronizes debug events between multiple components
JTAG and SWD Interface
The DAP controller supports either a JTAG or SWD interface for connecting to the external debug probe. JTAG uses a 4-pin interface while SWD uses only 2 pins. SWD provides equivalent debug capabilities and is the preferred option in Cortex-M devices due to lower pin count.
DIA Packet Processing
The DAP receives requests from the debugger using the Arm Debug Interface Access (DIA) protocol. This includes commands for reading and writing memory, accessing registers, setting breakpoints, and more. The DAP controller processes these packets and performs the requested operation.
Breakpoint and Watchpoint Control
The DAP manages up to 16 hardware breakpoints and 6 watchpoints. Breakpoints halt execution at a particular instruction address whereas watchpoints monitor data accesses to a memory address. The breakpoints and watchpoints are implemented in specialized registers and comparators in the Cortex-M core. The DAP provides the configuration interface to enable, disable, and set up these breakpoints and watchpoints.
System Memory Access
A key function of the DAP is to provide the debugger access to the system memory map including peripherals, registers, and RAM areas. The DAP includes an Address Resolution Unit that translates the debugger memory access requests to the appropriate bus protocol for the system interconnect.
System Register Access
In addition to memory access, the DAP allows read and write access to critical system registers in the Cortex-M processor and peripherals. This provides the debugger visibility into the configuration and state of the processor during program execution.
The DAP includes a Cross-Trigger Interface (CTI) which allows coordination of debugging events across multiple components in the system. For example, a breakpoint in the Cortex-M processor can trigger a breakpoint in another peripheral through this cross-trigger interface.
Cortex-M DAP Router
The DAP router is responsible for routing communications between the DAP controller and the internal APB interfaces in a Cortex-M system. This enables the DAP to access memory mapped resources in the system.
- Routes requests from DAP controller to appropriate APB interface
- Access port remapping for security
- AHB-AP protocol conversion
- APB bridging
The router connects the DAP controller to the system-level Advanced Peripheral Bus (APB) fabric. When the DAP controller issues a memory access request, the router will map this to the correct APB interface in the system based on the address mapping.
Access Port Remapping
For security purposes, the router can remap access port addresses to prevent access to restricted areas of the memory map by unauthenticated debug requests. This is configured using the ARM Debug Authentication (DAUTH) interface.
The DAP router handles any protocol conversion required between the DAP controller and the APB interfaces. This includes converting the AHB-AP protocol used by the DAP to the APB protocol used in the system interconnect.
In multiple APB domain systems, the router implements APB bridging functions to forward transactions between the APB domains. This allows the DAP to access resources across different APB buses.
Cortex-M DAP Interconnect
The DAP interconnect refers to the system level bus architecture and interfaces that enable communication between the DAP modules and the rest of the system.
Key Interconnect Buses
- AHB-AP – Main DAP bus for memory access requests
- APB – Peripheral interconnect bus
- AXI – Optional high-performance interconnect bus
The AHB-AP bus is used for memory access requests from the DAP controller to the system memory map. It is a customized version of the AMBA AHB protocol optimized for debug operations. The DAP router handles conversion between AHB-AP and APB protocols.
The APB interface provides access to peripheral device registers in the system. The DAP router maps DAP memory requests to the appropriate APB peripherals based on the address mapping.
Some Cortex-M systems also support connection over the AMBA AXI bus for high speed access to memory and peripherals during debug operations. The use of AXI is optional and not all Cortex-M devices include a DAP-AXI bridge.
To prevent unauthorized access and protect on-chip debug resources, the Cortex-M DAP includes debug authentication capabilities using the ARM Debug Authentication module (DAUTH).
- Uses 256-bit symmetric authentication key
- Debugger provides cryptographic signature with each request
- DAUTH module authenticates signature before allowing DAP access
- Keys are stored in on-chip ROM table
An encrypted signature based on a shared secret key is generated by the debugger and included with DAP requests. The DAUTH module uses the same secret key stored in on-chip ROM to authenticate the signature before allowing the request to proceed. Invalid requests are blocked providing security against unauthorized access.
ROM Table Programming
The ROM table stores the secret authentication keys provisioned during device manufacturing. The keys can be programmed by the manufacturer using fence controllers to securely blow fuses in the ROM table area. This prevents any external access for reading or modifying the keys.
DAP Usage in Cortex-M Devices
The Cortex-M DAP architecture outlined in this article is implemented in silicon across the range of Cortex-M processor cores to provide standardized debug capabilities. The DAP is widely used for development, debugging, and testing of Cortex-M based microcontroller devices.
Debug probes from companies like Segger, STLink, and ARM connect to the Cortex-M DAP interface through JTAG or SWD and leverage these debugging features. Debug probes handle the JTAG/SWD protocol and DAP packet communication so developers can access a common set of debugging commands.
Software debuggers and IDEs such as GDB, Keil MDK, and IDEs integrate with the DAP architecture using adapters. This enables a consistent debugging experience across Cortex-M vendors and platforms by leveraging the standard DAP capabilities.
The infrastructure for debug access also enables detailed testing and validation of Cortex-M devices during production using automated test equipment. Manufacturers use DAP interfaces and commands extensively for chip-level and system-level production testing.
Device vendors implement additional optimizations in the DAP architecture to improve debug performance and reduce system impact.
Debug Port Optimizers
Debug Port Optimizers provide smart caches and buffers to reduce debug command traffic for frequently used operations like memory read/write. This improves throughput and minimizes system bus and memory access impact.
Post-silicon Debug Features
Vendors enhance DAP capabilities for post-silicon validation of silicon re-spins using JTAG boundary scan controllers to deeply probe internal processor signals not available through the basic DAP interface.
Idle logic, clock gating, and power domains minimize power consumption of the DAP modules when not actively being used. This reduces the static power overhead of including debug capabilities.
This article provided an overview of the Arm Cortex-M DAP architecture and how it enables effective and standardized debugging of Cortex-M processors. The DAP provides a robust set of capabilities through its controller and interconnect interfaces including breakpoints, watchpoints, memory access, and registers access. Advanced features such as debug authentication and cross-triggering further enhance debug security and system visibility. Adoption of the DAP architecture has simplified development tool integration across the Cortex-M ecosystem.