The Cortex-M3 processor provides multiple clock control features that allow significant power savings by slowing or stopping clocks when parts of the system are idle. Careful use of these features can extend battery life in portable applications or reduce heat and energy use in plugged-in systems. This article provides an overview of the clock control capabilities in the Cortex-M3 and guidance on how to take advantage of them in your applications.
Cortex-M3 Clocking System
At a high level, the Cortex-M3 clocking system consists of the main system clock driven by an on-chip or external oscillator, a Phase Locked Loop (PLL) that multiplies this base clock frequency, and the Nested Vectored Interrupt Controller (NVIC) which controls clocking to the CPU core and peripherals. The PLL allows the CPU to run at a higher frequency than the base system clock, which is useful for improving performance. The NVIC gates these clocks on and off to different parts of the system when they are not needed.
The main system clock can be driven by an on-chip RC oscillator, an on-chip crystal oscillator, or an external clock source. The RC oscillator is the least accurate but requires no external components. The crystal oscillator is more accurate but requires an external crystal. Finally, providing an external clock allows the most flexibility and accuracy.
Phase Locked Loop (PLL)
The Cortex-M3 PLL multiplies the frequency of the system clock to provide a faster clock to the CPU core. This allows the CPU to run at a higher frequency without needing an equally fast system clock. The PLL takes the system clock as its reference and can multiply it by up to 512x to generate the CPU clock. When the PLL is disabled, the CPU runs at the system clock frequency.
Nested Vectored Interrupt Controller (NVIC)
The NVIC controls clocking to the CPU core and peripherals based on power management settings. It can gate these clocks on and off to put parts of the system into sleep or low power modes. The NVIC has fine-grained control and can stop the clock to individual peripherals. It also handles waking up system components based on interrupts.
Low Power Modes
The Cortex-M3 supports several low power modes that shut down clocks to unused parts of the system. These include Sleep, Deep Sleep, and Deep Power Down modes. Using these low power modes can significantly reduce energy consumption when the CPU and peripherals are idle.
In Sleep mode, the system clock to the CPU is gated off, stopping operation. However, the PLL and system peripherals remain active. Sleep mode stops CPU execution and related power use but allows quick wake up since the system clock remains enabled. peripherals can also continue operating in this mode.
Deep Sleep Mode
Deep Sleep mode gates the clocks to the CPU, peripherals, and PLL. This stops almost all internal activity for the lowest power consumption. However, the system clock remains active. Deep Sleep has higher wakeup latency than Sleep mode since the PLL and peripherals need to be reinitialized.
Deep Power Down Mode
Deep Power Down mode completely shuts down the internal voltage regulators to minimize power use. This stops the system clock and removes power from the entire device except for a few wake up sources. Wakeup latency from Deep Power Down is highest since the entire chip needs to restart. This mode minimizes power use but prevents any peripherals or processing from occurring.
To make effective use of the Cortex-M3 sleep and low power modes, clocks to unused peripherals should be gated off whenever possible. The NVIC provides clock gating control registers to enable and disable clocks to each peripheral individually.
Peripheral Clock Gating
In the NVIC, each peripheral has a bit in the clock gating registers that enables or disables clocks to that peripheral. Setting a peripheral’s bit disables its clock, gating power and preventing operation. Clearing the bit enables the clock and allows the peripheral to function. Disabling unused peripherals prevents wasted power from clocks driving powered down circuitry.
PLL Power Down
When the CPU does not need to run at high frequencies, the PLL can be powered down to save energy. This reverts the CPU clock back to the system clock speed. The PLL takes significant power even when idle, so disabling it saves power when the higher CPU frequency is not required.
Oscillator Power Down
In Deep Power Down mode, even the system clock oscillators can be powered down to maximize power savings. This completely removes power from all internal clock generation. When using the on-chip RC or crystal oscillators, powering down the oscillators saves significant power compared to leaving them running.
Wake Up from Low Power
The Cortex-M3 uses interrupts to wake up from its low power modes. When entering a low power mode, an interrupt event or other wake up trigger can be selected to cause the system to resume normal operation. The NVIC handles masking interrupts as necessary and restoring clocking when waking up.
Any enabled interrupt can wake the system from Sleep or Deep Sleep modes. For example, a timer interrupt could periodically wake the CPU to perform tasks, with the system going back to sleep in between. Alternatively, a communication peripheral interrupt could wake the system when data is received.
External Wake Up
In Deep Power Down mode, only external wake up pins can wake the system since internal clocks and peripherals are powered down. An external hardware trigger like a power button press or other system event can wake up the chip via these dedicated wake up pins.
PLL and Clock Restoration
When waking from Deep Sleep or Deep Power Down modes, the NVIC must re-enable the PLL and system clocks so the CPU and peripherals can resume operation. This restart sequence adds some latency before the system is fully operational again. Proper handling of wake up events and clocks minimizes this time.
Power Optimization Tips
Here are some tips for using the Cortex-M3 low power modes and clock options to optimize power efficiency in your application:
- Use Sleep mode for short idle periods to quickly stop CPU activity while allowing fast wake up.
- Enter Deep Sleep for longer idle periods to shut down more of the system.
- Power down the PLL when CPU performance is non-critical.
- Gate clocks to all unused peripherals even during active use.
- Configure timer or communication interrupts to wake the system when needed.
- Use Deep Power Down mode during extended idle periods and provide a wake up pin.
- Manage wake up event latency by minimizing restart time.
- Combine sleep modes and clock gating aggressively to maximize power savings.
With careful use of its sleep modes and clock control capabilities, significant power savings can be achieved on the Cortex-M3 even for systems with activity and peripheral use. following best practices allows extending battery life and reducing energy use.
Here is an example of how these Cortex-M3 features could be used in a real application to optimize power efficiency:
An IoT sensor device that transmits data packets over WiFi every 60 seconds but is idle most of the time. It uses a Cortex-M3 MCU running at 72 MHz system clock with the PLL enabled for a 120 MHz CPU clock. Peripherals used are WiFi, UART, Timer, and ADC.
When actively sampling the ADC and transmitting WiFi, all peripherals and PLL are enabled. UART and Timer interrupts handle the packet transmission timing. Constant ADC sampling and WiFi use consume significant power.
Light Sleep Mode
In between transmissions, the system enters Sleep mode, gating the CPU clock to stop processor activity. The peripherals and PLL remain active. The Timer interrupt brings the system back to active mode for the next transmission. Sleep mode reduces power consumption while allowing quick wakeup.
Deep Sleep Mode
For idle periods longer than a minute, the system enters Deep Sleep mode, disabling the PLL and gating all peripheral clocks. Only the Timer runs to wake the system after 60 seconds. Deep Sleep minimizes power consumption during extended idle periods.
Deep Power Down Mode
If no transmissions occur for an extended time, the system enters Deep Power Down mode, fully powering down the clocks and voltage regulators. Only a motion sensor interrupt can wake the system from Deep Power Down. This eliminates quiescent power draw.
Optimizing the various low power modes during activity and idle results in significant power savings compared to a continuously active system. The Cortex-M3 sleep and clock control capabilities enable this power efficient operation.
The Cortex-M3 provides flexible clock control options and multiple low power modes to enable power optimization for many different applications. Taking advantage of these features requires careful management of clock gating, wake up events, and latency. With good use of sleep modes during idle periods and disabling unused clocks, large reductions in power consumption can be achieved. Following the tips and guidelines in this article will help you leverage the Cortex-M3 to build an efficient, power saving system.