The Cortex-M System Design Kit supports a range of bus protocols that allow the Cortex-M processor to interface with peripheral devices and external memory. Selecting the right bus protocol is an important design consideration that impacts performance, power consumption, and ease of integration with hardware blocks.
The Advanced Microcontroller Bus Architecture (AMBA) AHB-Lite protocol is a widely used bus standard for on-chip communication. It provides a high-performance interface between the processor and on-chip memories and peripherals. Some key features of AHB-Lite are:
- Supports burst transfers for efficient data movement
- Pipelined operation for high throughput
- Single edge clocking scheme for ease of integration
- Separate read and write data buses for concurrency
- Configurable data bus width (32/64/128 bits)
- Uses a centralized arbitration scheme
- Support for easy addition of wait states and data bus parking for slow peripherals
In the Cortex-M System Design Kit, the AHB-Lite protocol can be used to connect the processor to tightly coupled memories, external bus interfaces, APB bridge, and other system components. It is a good fit for high performance designs due to its simplicity and efficiency.
The AMBA APB protocol is intended for interfacing to low bandwidth peripherals in a Cortex-M system. It trades off performance for smaller interface logic and lower power. Key attributes of APB are:
- Operates at a lower clock frequency derived from the system bus clock
- Supports only sequential address-data transfers
- Data bus width fixed at 32 bits
- Allows peripherals to insert wait states
- Higher area efficiency compared to AHB-Lite interface
- Separate enable signals for read and write accesses
- All transfers are only 1 or 2 cycles long
In the Cortex-M System Design Kit, APB can be used for attaching UARTs, timers, I/O ports, watchdog timers, and other peripheral devices. The Cortex-M processor connects to the APB bus through an AHB-APB bridge module.
The AMBA AXI protocol builds on top of AHB and APB to provide even higher performance, more robust control semantics, and ease of integration. Key features offered by AXI are:
- Separate address/control and data phases for transfers
- Support for unaligned data transfers using byte strobes
- Burst based transactions with only start address issued
- Out-of-order transaction completion and interconnect pipelining
- Allows issuing multiple outstanding addresses
- Wide range of burst types like WRAP, FIXED, INCR supported
- Configurable data bus width up to 1024 bits
- Uses side-band signals for quality of service
The extensive functionality of AXI comes at the cost of higher logic utilization and power consumption. Hence it is most suitable for high performance designs where multiple masters need low latency access to peripherals and memory. The Cortex-M System Design Kit provides an AXI interconnect module to leverage the benefits of this protocol.
Wishbone is an open source, patent-free interconnect standard meant for SoC integration. It offers similar functionality as AMBA at lower gate count by stripping away some advanced features. Salient aspects of the Wishbone protocol are:
- Supports both single and block read/write transactions
- Variable data bus width, typically 8/16/32/64 bits
- Centralized/distributed arbitration allowed
- Multiple masters can access the bus through a shared interconnect
- Simple handshake signaling using STB/ACK
- Modular pipelined interconnect for high throughput
- Single clock domain simplifies timing closure
Wishbone provides a good balance between performance, area, and ease of use. It can be deployed to connect the Cortex-M processor to a range of system components like data/instruction memory interfaces, DMA controllers, and custom hardware accelerators.
The CoreConnect PLB bus developed by IBM is similar in spirit to AMBA. It is intended to provide a high performance path between the processor and peripherals. Major capabilities offered by PLB are:
- Pipelined operation allows new transfers during every clock cycle
- Burst transfers optimize data movement
- Separate read and write data buses
- Configurable data bus width from 32 to 128 bits
- Supports multiple masters through centralized arbitration
- Quality of service signals to differentiate transfer types
- Allows insertion of wait states by slaves
The PLB bus offers predictable latency and high bandwidth for on-chip communication. It can be deployed in Cortex-M designs requiring a proven, widely used bus standard.
Arm CoreLink NIC-400 Network Interconnect
Arm’s CoreLink NIC-400 offers a state-of-the-art network on chip (NoC) interconnect solution. It provides extremely high bandwidth communication between multiple masters and slaves. Key highlights are:
- Peak bandwidth of 400 GBps through 16 concurrent 64-bit links
- Meshed topology provides multiple paths between endpoints
- Wormhole switched packet transfers
- Quality of service and traffic class prioritization
- Extensive power management capabilities
- Configurable topology and routing
- AMBA AXI plug-and-play compatibility
The NIC-400 NoC can future-proof SoC designs by providing scalable on-chip communication as complexity increases. Its excellent performance makes it suitable for integrating high-speed components like GPUs, DSPs, and hardware accelerators in Cortex-M based systems.
Custom Bus Protocols
Along with standard bus protocols, the Cortex-M System Design Kit allows creating custom bus interfaces to connect to application-specific peripherals and IP blocks. This requires adhering to the processor’s bus protocol specifications, but gives the flexibility to tailor the interface for particular requirements.
Some examples of custom bus protocols are:
- Minimized bus interface for a dedicated hardware accelerator
- Custom packet-based protocol for networking subsystems
- Low latency bus for tightly coupled memory
- Simplified bus with basic flow control for low power IoT edge nodes
Careful optimization of custom bus protocols can result in lower gate count, power savings, reduced latency, and better performance compared to standard solutions.
In summary, the Cortex-M System Design Kit supports a diverse set of bus protocols catering to different application needs. AHB-Lite, APB, and AXI cover the spectrum for on-chip communication requirements. Wishbone provides a flexible open-source alternative. PLB offers compatibility with legacy designs. Cutting edge solutions like NIC-400 enable building advanced heterogeneous systems. And custom bus protocols allow further optimization for specific use cases. With this comprehensive protocol support, the Cortex-M System Design Kit enables creation of efficient and high-performance system architectures.