The Cortex-M3 is an ARM processor core designed for embedded applications. It has a flexible memory interface that allows it to connect to different types of memory devices and configurations. The key features of the Cortex-M3 memory interface include:
Tightly Coupled Memory Interface
The Cortex-M3 contains up to 64KB of fast on-chip Tightly Coupled Memory (TCM) that can be used for time critical code and data. This TCM memory is single cycle access for maximum performance. It is split into separate instruction and data TCM areas. The Cortex-M3 TCM interface connects directly to the processor core and does not go through the main system bus, allowing zero wait state access.
External Bus Interface Unit
The External Bus Interface Unit (EBIU) controls access to external memories and peripherals. It provides interfaces for:
- External flash memory
- External SRAM
- External devices
The EBIU contains configuration registers to set up the types, sizes, timing and interfaces for the external memories. This provides flexibility in connecting different memory technologies like NOR and NAND flash or mobile DDR SDRAM.
Flash Memory Interface
The flash memory interface supports parallel NOR flash and NAND flash. It includes configurable wait states and timing parameters to match different flash memory speeds. It also includes flash programming and erase control logic.
SRAM Memory Interface
The SRAM interface supports connecting parallel external SRAM with configurable data bus width (8-bit to 32-bit) and programmable wait states. It can be used for code and data storage.
The ROM interface allows connecting parallel ROM devices for boot code. Similar to SRAM, it has configurable bus width and wait states.
AHB Bus Matrix
The EBIU interfaces to the Cortex-M3 core via an AHB bus matrix. This provides a flexible interconnect between the EBIU, core and nested vector interrupt controller. It allows simultaneous access to memories and peripherals with programmable arbitration.
Memory Protection Unit
The Cortex-M3 includes an optional Memory Protection Unit (MPU) to improve software robustness by limiting memory accesses. The MPU divides memory into up to 8 regions and defines access permissions (privileged/user, read/write) for each region. This prevents unauthorized access to code and data in memory.
The Cortex-M3 memory map is flexible based on the system design requirements. Typical embedded configurations map Flash memory at 0x0000_0000, SRAM at 0x2000_0000 and peripherals at 0x4000_0000. The TCM memories can be mapped to any 32KB aligned address. The flexible EBIU and MPU allow tailoring the memory map to the system needs.
Memory Access Types
The Cortex-M3 supports four different types of memory accesses:
- Byte access – Single 8-bit byte read/write
- Halfword access – 16-bit halfword read/write
- Word access – 32-bit word read/write
- Atomic bit operations – Set, clear, toggle single bits in memory
These provide efficient access for different data types stored in memory. The atomic bit operations are useful for bit flags and semaphores.
Harvard vs Von Neumann Architectures
The Cortex-M3 uses a modified Harvard architecture. This separates instruction and data memory into two independent buses. This allows simultaneous fetch of instruction and data for higher performance. In contrast, Von Neumann architecture uses a single shared memory bus for instructions and data.
The Cortex-M3 supports both little endian and big endian memory accesses. Endianness refers to the byte ordering of data in memory. Little endian stores the least significant byte at the lowest address. Big endian stores the most significant byte first. Endianness is configured at design time based on system requirements.
Deterministic Memory Latencies
The Cortex-M3 uses static RAM technology for caches and TCM memory. This provides deterministic access times, unlike cache based processors that have variable latency. Deterministic latency simplifies real-time software development. The loop timings and interrupt latencies are predictable.
Memory barriers are instructions that force synchronization of memory operations. The Cortex-M3 supports Data Memory Barrier (DMB) and Data Synchronization Barrier (DSB) instructions. These ensure that memory reads/writes are completed before starting new memory accesses. Barriers prevent unwanted reordering of operations by the processor pipeline.
Memory regions can be assigned attributes like cacheable, bufferable, shareable etc. This controls cache and buffer use for the region. Setting appropriate attributes is important for real-time software to avoid unpredictability caused by caching.
In summary, the Cortex-M3 memory interface provides a flexible set of capabilities to connect to different memory technologies, customize the memory map, access memory efficiently using the Harvard architecture and support real-time determinism. The combination of TCM, bus matrix, MPU and EBIU with configurable timing parameters and attributes allows optimal integration of memories and peripherals in embedded system designs.