The bus interface in the Cortex-M3 processor provides the connection between the processor core and external memories and peripherals. It manages all bus transactions like read, write and fetch operations. The Cortex-M3 bus interface is designed for low power consumption and high performance.
Overview of Cortex-M3 Bus Interface
The Cortex-M3 processor has a three-layer bus interface consisting of the system bus matrix, peripheral buses and memory buses. The system bus matrix connects the processor core to the peripheral and memory buses. It can connect up to 64 peripherals and contains arbiters to handle contention between simultaneous bus access requests.
The peripheral buses include the Advanced High-performance Bus (AHB) and the Advanced Peripheral Bus (APB). The AHB is a high-speed bus for connecting to high bandwidth peripherals like external memory interfaces. It supports burst transactions and pipelining for high throughput. The APB is a lower speed bus for low bandwidth peripherals like timers, watchdogs etc. It only supports simple read/write transactions.
The memory buses connect the system bus matrix to on-chip SRAM, on-chip Flash memory and external memory interfaces. These include the Internal Memory Bus (IMB), Instruction Memory Bus (IMB), Data Memory Bus (DMB) and External Memory Bus (EMB). The IMB connects to internal SRAM while the IMB and DMB connect to internal Flash memory. The EMB connects to external memory interfaces like SRAM, Flash, SDRAM etc.
AHB Bus Interface
The AHB bus interface runs at the full clock speed of the Cortex-M3 core and is used for high performance peripherals. It supports:
- Burst transfers for memory accesses
- Split transactions for non-blocking transfers
- Pipelined operation for high throughput
- Multiple bus masters
- Up to 16 peripheral connections
The AHB has separate address/control and data buses for efficient transfers. Read and write data can be transferred in a single cycle if the slave peripheral responds in time. The AHB interface has a bus arbiter to decide which bus master gets access if multiple masters try to access the bus simultaneously.
AHB Bus Transfers
The AHB supports bursting transfers for memory accesses. In a burst, the address is given only for the first word and subsequent words are read or written to sequential addresses. This saves bus cycles when accessing sequential memory locations. Burst transfers are useful when caching instructions and data in tightly coupled memories.
The AHB also uses split transactions to avoid stalling the bus during multi-cycle transfers. When the slave indicates it cannot respond immediately, the bus is released and the transfer continues when the slave is ready. This prevents the bus from remaining idle during latent slave responses.
Pipelined operation allows a new transfer to begin before the previous transfer has completed. This improves bus utilization and efficiency.
AHB Bus Arbitration
The AHB arbiter manages access to the bus when multiple masters try to access it simultaneously. It supports both fixed priority and round-robin arbitration schemes.
In fixed priority arbitration, each master has a static assigned priority. The master with the highest priority gets access to the bus. If two masters have the same priority, a round-robin scheme is used to share access between them.
In round-robin arbitration, the masters take turns using the bus in a circular order. Each master gets a slice of time on the bus before releasing it to the next master. This prevents starvation and provides fair access.
APB Bus Interface
The APB bus interface is used for lower bandwidth peripherals like timers, watchdog, UARTs, I2C etc. It has the following features:
- Operates at a fraction of the system clock frequency
- Only simple read/write transfers supported
- All transfers are 32-bit wide
- Up to 16 peripherals supported
- Bus access controlled by a single unit
The APB runs at a lower clock frequency derived from the system clock using a clock divider. This reduces power consumption in the slower peripherals. Only simple data read/write transfers are supported in a single bus cycle. There is no burst or pipelined operation like in the AHB.
The Cortex-M3 processor contains dedicated bus interfaces to internal and external memories.
Internal Memory Bus
The Internal Memory Bus (IMB) connects the processor core to internal SRAM memory. It is 64-bit wide allowing 8-byte fetch and load/store transfers to/from the SRAM. The IMB runs at the same frequency as the processor core so SRAM accesses have minimal latency.
Instruction Memory Bus
The Instruction Memory Bus (IMB) is used to fetch instructions from internal Flash memory. Instruction fetches are 32-bit wide over the IMB. It also runs at the full processor core clock speed to prevent wait states during instruction fetch.
Data Memory Bus
The Data Memory Bus (DMB) is used for data reads and writes to internal Flash memory. It is 32-bit wide and connects to separate data and instruction ports of the Flash memory. This allows simultaneous instruction fetch and data access to internal Flash.
External Memory Bus
The External Memory Bus (EMB) connects the processor to external memory interfaces like SRAM, SDRAM, Flash etc. The EMB has the same signalling protocols as the AHB bus to ensure compatibility. It can be up to 64-bit wide for high bandwidth access to external memory.
The EMB contains programmable timing control registers to adapt to different external memory speeds. This prevents wait states being incurred when accessing slower external memories.
Bus Interface Units
There are several bus interface units that generate the signals required by the various buses:
- AHB Lite Master Interface – Connects processor core to AHB bus
- AHB Lite Slave Interface – Connects AHB peripherals to AHB bus
- APB Bridge – Connects AHB to APB bus and acts as a bridge
- External Memory Interface – Generates signals for external memory bus
- SRAM/Flash Interface – Generates signals for SRAM and Flash buses
These interface units contain all the bus signaling logic like driving address, data, control signals, bus arbitration etc. This keeps the bus complexity out of the processor core and peripherals.
In summary, the Cortex-M3 bus interface provides flexible high-performance connectivity between the processor core, memories and peripherals. Key features include:
- AHB bus for high bandwidth peripherals with bursting and pipelining capability
- APB bus for lower bandwidth peripherals
- Dedicated buses to internal SRAM and Flash memories
- External memory bus with configurable timing
- Bus arbitration and protection units
- Modular bus interface units to simplify implementation
These features enable the construction of highly integrated and optimized Cortex-M3 systems with flexible memory and peripheral connectivity tailored for power efficient operation.