The ARM Cortex-M3 processor has two main operational modes – Thread Mode and Handler Mode. Understanding these two modes is key to utilizing the Cortex-M3 processor effectively in embedded applications.
Thread Mode is the default operational mode in Cortex-M3. All application software code executes in Thread Mode. This includes the main() function and any other application code. When the processor resets, it always starts in Thread Mode.
In Thread Mode, the processor can access both main stack and process stack. The Main Stack is used for exception handling and contains stack frames for each exception handler. The Process Stack contains stack frames for application code and PSP (process stack pointer) points to the current top of this stack.
Application data is accessed using standard operational registers like R0-R12. Thread Mode has access to full CPU registers without any privilege restrictions. It can freely manipulate the MSP, PSP, and other CPU registers.
By default, Thread Mode does not have access to fault handling registers or privileged CPU operations like changing execution priority, interrupt handling, etc. An attempt to access any privileged resource results in a fault. This provides protection and isolates application code from critical system code.
Features of Thread Mode
- Default operational mode on reset
- Application software executes in Thread Mode
- Can access Main Stack and Process Stack
- Uses PSP register to access Process Stack
- Full access to general purpose registers like R0-R12
- No access to privileged registers or resources
- Attempting to access protected resource causes exception/fault
Handler Mode is used to service exceptions and interrupts. All exception handlers execute in Handler Mode. When an exception occurs, the processor switches from Thread Mode to Handler Mode to run the exception handler routine.
In Handler Mode, the processor uses the Main Stack. The MSP (main stack pointer) register is used to access this stack. Handler Mode has access to all CPU registers without any limitations. It can freely manipulate the stack pointers, control registers, and other privileged resources.
Handler Mode code executes at a higher privilege level compared to Thread Mode. This allows exception handlers to implement fault handling, interrupt processing, task switching, and other critical operations safely and securely.
After completing exception processing, the handler code returns back to Thread Mode using the special EXC_RETURN opcode. This performs the required context switching and restores the application state to seamlessly resume normal operation.
Features of Handler Mode
- Used to service exceptions and interrupts
- Exception handlers execute in Handler Mode
- Uses Main Stack accessed via MSP register
- Full access to all CPU registers and resources
- Executes at a higher privilege level than Thread Mode
- Allows implementing fault handlers, task switching, etc.
- Returns to Thread Mode using EXC_RETURN opcode
Thread vs Handler Mode
Here is a comparison between the two modes:
|Feature||Thread Mode||Handler Mode|
|Entry||On reset||On exception entry|
|Exit||On exception||Using EXC_RETURN|
|Stack||Process and Main||Only Main|
- Thread Mode is used to run normal application code
- Handler Mode is used to run privileged exception handlers
- Thread Mode provides isolation while Handler Mode provides full access
- Mode transition occurs on exception entry/return
- Understanding the modes is key to Cortex-M3 usage
Mode Switching Sequence
When an exception occurs, the processor automatically switches from Thread Mode to Handler Mode by performing the following steps:
- Saves EXC_RETURN code on Main Stack
- Saves current stack pointer (PSP) on Main Stack
- Changes to Handler Mode
- Switches to Main Stack
- Updates MSP to current Main Stack pointer
- Jumps to exception handler address
On exception return, the reverse operation restores the Thread Mode context:
- Restores MSP from Main Stack
- Returns to Thread Mode
- Restores PSP from Main Stack
- Pops and executes EXC_RETURN code
- Resumes execution in Thread Mode
This careful saving and restoring of stack pointers and privilege states ensures seamless transition between the two modes during exception processing.
Some example use cases of Thread and Handler modes are:
- Application Code – Runs in Thread Mode using Process Stack and R0-R12 registers
- System Timer ISR – Handler Mode used to quickly save context and program timer for next interval
- Memory Fault – Handler Mode used to isolate fault and take appropriate recovery action
- Task Switching – Handler Mode used to save and restore task contexts during RTOS scheduling
- Supervisor Call – Optionally switch to Handler Mode to perform privileged operation
Properly utilizing both modes as per application requirements is key to designing robust and secure Cortex-M3 based systems.
Thread Mode Priority Levels
Cortex-M3 implements configurable priority levels within Thread Mode to allow differentiation between different application threads in an RTOS context. This is enabled using the BasePRI register.
BasePRI can be set to specify the threshold priority level from 0 to 255. All application threads with priority below this level get temporarily disabled when BasePRI is set to higher level.
This allows execution of high priority thread code uninterrupted by lower priority application threads. BasePRI is automatically cleared on exception entry and restored on exception return.
Using BasePRI allows efficient application level context switching without incurring the full overhead of exception processing.
- Cortex-M3 has two distinct modes – Thread and Handler
- Thread Mode runs normal application code
- Handler Mode runs privileged exception handlers
- Each mode has separate stack, registers and privilege
- Mode transition occurs during exception processing
- Understanding the modes is key to utilizing Cortex-M3 capabilities
The dual mode architecture provides robust exception handling, application isolation and high performance. Studying the detailed operation of both modes allows developers to harness the full power of Cortex-M3 in their embedded system designs.