Holly Lindsey

57 Articles

Cortex-M3 Memory Access Constraints with Caches and Shared Memory

The Cortex-M3 processor has advanced memory access capabilities through the use of caches and shared memory regions. However, these features

Holly Lindsey 6 Min Read

What are the two operational modes in ARM Cortex M3?

The ARM Cortex-M3 processor has two main operational modes - Thread Mode and Handler Mode. Understanding these two modes is

Holly Lindsey 7 Min Read

Using BX and BLX Instructions Correctly in Thumb Code

When writing assembly code for ARM Cortex chips using Thumb instruction set, the BX and BLX instructions allow you to

Holly Lindsey 16 Min Read

Ensuring Thumb Mode Stays Enabled in Cortex-M3

When programming for the Cortex-M3 processor, it is important to keep the processor in Thumb mode rather than ARM mode.

Holly Lindsey 12 Min Read

What is the Current Program Status Register (CPSR) in Arm Cortex-M?

The Current Program Status Register (CPSR) in Arm Cortex-M is a 32-bit register that contains condition code flags, interrupt disable

Holly Lindsey 9 Min Read

Difference between arm7, arm9, arm11 and arm cortex

The ARM architecture refers to a family of reduced instruction set computing (RISC) processors that are widely used in embedded

Holly Lindsey 12 Min Read

What are the interrupts and exceptions in Cortex-M3?

The Cortex-M3 processor has a number of interrupts and exceptions that allow it to respond to events and handle errors

Holly Lindsey 8 Min Read

Manually Stacking Registers for Cortex-M Context Switching

Context switching on Cortex-M microcontrollers requires manually saving and restoring register contents when switching between tasks. This involves stacking key

Holly Lindsey 7 Min Read

Stack Frame Layout During Cortex-M Interrupts

When an interrupt occurs on a Cortex-M processor, the processor pushes registers onto the stack to save the current state

Holly Lindsey 7 Min Read

Implementing a Round-Robin Scheduler on Cortex-M

A round-robin scheduler is a scheduling algorithm that sequentially cycles through a list of tasks, giving each task a slice

Holly Lindsey 5 Min Read

Cortex-M Exception Handling and Return Mechanism

The Cortex-M processor implements robust exception handling capabilities to respond to events like exceptions, interrupts, and faults during program execution.

Holly Lindsey 6 Min Read

STM32F1 (Cortex-M3) Boot from RAM Behavior

The STM32F1 microcontroller based on the Cortex-M3 core provides the ability to boot from RAM instead of flash memory. This

Holly Lindsey 6 Min Read
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