The Current Program Status Register (CPSR) in Arm Cortex-M is a 32-bit register that contains condition code flags, interrupt disable bits, current processor mode bits, and other status and control information. The CPSR allows the processor to keep track of the current execution state of a program and controls how instructions are executed. It plays a crucial role in exception and interrupt handling in Cortex-M processors.
Overview of CPSR
The CPSR is a key component of the Arm architecture present in all Cortex-M processor cores. It contains several important fields that govern the execution of a program:
- Condition code flags (N, Z, C, V) – indicate the results of arithmetic and logical instructions
- Current processor mode bits – determine the operating mode of the core like Thread, Handler, etc.
- Interrupt disable bits – allow interrupts to be disabled
- Stack alignment control bit
- Extended thumb state bit
The CPSR register can be read using the MRS instruction and written to using the MSR instruction. The processor automatically updates the appropriate CPSR fields during exception entries and returns. By controlling the CPSR fields, the core’s execution can be altered.
CPSR Condition Code Flags
The 4 condition code flags in the CPSR provide information on the results of arithmetic and logical instructions executed by the core. These bits are automatically set or cleared by instructions without explicit programmer intervention. The flags are:
- Negative (N) flag – Set if the result of an instruction is negative
- Zero (Z) flag – Set if the result of an instruction is zero
- Carry (C) flag – Set if an instruction results in a carry condition
- Overflow (V) flag – Set if an instruction results in an overflow condition
The condition flags are used to evaluate conditional execution in the processor. Based on the values of the flags, a conditional instruction can either execute or skip execution. This allows code to perform conditional branching, comparisons, andLOOPs without explicitly evaluating boolean conditions.
CPSR Processor Mode Bits
The processor mode bits in the CPSR determine the current operating mode of the Cortex-M core. The Cortex-M supports 8 modes with each mode having its own stack pointer, privilege level and available resources:
- User (USR) mode – Used for normal program execution
- Fast Interrupt (FIQ) mode – Supports fast interrupts
- Interrupt (IRQ) mode – Used for general purpose interrupts
- Supervisor (SVC) mode – A protected mode for the OS kernel
- Abort mode – Entered on data or instruction aborts
- Undefined mode – Triggered by undefined instructions
- System (SYS) mode – Privileged task for OS use
- Debug (DBG) mode – Used for debugging
By switching the core to a particular mode, access to certain resources, registers and execution privileges can be controlled. This provides security and protects critical system resources.
CPSR Interrupt Disable Bits
The CPSR contains 2 interrupt disable bits that allow interrupts to be masked in the system:
- I bit – Disables IRQ interrupts when set
- F bit – Disables FIQ interrupts when set
Setting these bits prevents interrupts from triggering unintended context switches and corrupting critical data structures. The bits can be set or cleared under software control to enable or disable interrupts.
CPSR Stack Alignment Bit
The S bit or stack alignment bit in the CPSR controls whether the stack pointer should be aligned to a 4-byte or 8-byte boundary on exception entry. On reset, the Cortex-M aligns the stack pointer to 4-bytes. Setting the S bit causes 8-byte alignment which is useful when using extended floating point instructions.
CPSR Thumb State Bit
The T bit or Thumb state bit indicates whether the processor is currently executing in Arm or Thumb state. Cortex-M cores support both Arm and Thumb instruction sets. The T bit determines which instruction set is active at any given time.
Reading and Writing the CPSR
The CPSR can be directly read and written in software using the MRS and MSR instructions. For example: MRS R0, CPSR ; Read CPSR into R0 MSR CPSR_f, R0 ; Write R0 flags into CPSR
However, access to the CPSR is restricted based on the current processor mode. Some CPSR fields like the mode bits cannot be changed freely in software.
CPSR and Exception Handling
One of the most important uses of the CPSR is in exception and interrupt handling in Cortex-M cores. Whenever an exception or interrupt occurs, the processor automatically:
- Saves the current CPSR value on the stack
- Updates the CPSR mode bits to enter the handler mode
- Pushes the return stack pointer onto the stack
This switches the core to a privileged handler mode and stacks the appropriate context. When the handler finishes, it pops the return stack pointer and restores the original CPSR using the MSR instruction to resume the interrupted program.
Typical CPSR Usage
Here are some typical use cases for manipulating the CPSR during programming:
- Check negative/zero flags to evaluate comparisons and conditions
- Set interrupt disable bits to protect critical sections from preemption
- Switch to system mode with specific stack pointer for OS usage
- Examine mode bits to check current privilege and access level
- Restore original CPSR value after handling exceptions and interrupts
Care must be taken when altering the CPSR as it can drastically change the state of the core. Restricted mode changes and bit masking is often used.
CPSR Registers in Cortex-M
The Cortex-M family of processors contains multiple CPSR registers:
- Main CPSR – The main 32-bit CPSR register discussed above
- PSP – Process Stack Pointer for Thread mode
- MSP – Main Stack Pointer for Handler mode
- PRIMASK – Masks interrupts
- FAULTMASK – Masks faults
- BASEPRI – Sets interrupt priority threshold
These auxiliary registers help extend CPSR functionality for stack management, priority handling and interrupt control in the Cortex-M cores.
CPSR Differences Across Cortex-M Generations
While the general layout and functionality of the CPSR is consistent across the Cortex-M product line, there are some differences between the various generations of cores:
- Cortex-M0/M1 – No stack alignment bit, limited modes
- Cortex-M3 – Added stack alignment, thumb-2 extension
- Cortex-M4 – Adds floating point extension
- Cortex-M7 – Supports double precision floating point
- Cortex-M23/M33 – Enhanced exception support
So newer cores extend the CPSR capabilities while maintaining backwards compatibility and the overall register layout.
CPSR vs xPSR
The xPSR is an extension of the CPSR available in Cortex-M cores to provide extra mode information. The xPSR contains all CPSR fields plus:
- ISR number field – Stores interrupt number for CMSIS APIs
- Exception number field – Stores exception cause number
This helps differentiate various interrupt sources and exceptions for improved debugging and handling in the Cortex-M architecture.
Conclusion
The CPSR is a crucial status register in Arm Cortex-M cores that governs major aspects of program execution flow, exceptions and interrupts. It contains condition flags, mode bits, disable bits and other fields that control the operational state of the processor. Understanding the layout and functionality of the CPSR is important for effectively programming Cortex-M based microcontrollers.
Some key points about the CPSR:
- Contains status flags, mode bits, and control fields
- Automatically updated during exceptions and interrupts
- Different modes have access to different resources
- Can be read/written in software via MRS/MSR
- Changes program flow, interrupt handling, privileges
- Extended by xPSR to provide debugging help
The CPSR is at the heart of Cortex-M processor implementations and being familiar with its workings is essential for embedded programmers and developers.