The Vector Table Offset Register (VTOR) is a key register in Arm Cortex-M series processors that controls the location of the vector table in memory. The vector table contains the reset value for the stack pointer and the exception vector entries which hold the addresses of interrupt service routines. By changing the VTOR, the vector table can be relocated to a different memory region. This provides flexibility in placing the vector table in read-only memory or RAM based on application requirements.
Overview of Vector Table in Cortex-M
On reset or power-up, the Cortex-M processor loads the initial stack pointer value and starts execution at the reset vector located at the start of the vector table. The vector table is an array of exception vectors, with each vector consisting of a 32-bit address pointing to an exception handler routine. For Cortex-M3 and M4, the vector table comprises up to 240 vectors and occupies up to 0x600 bytes of memory. For Cortex-M0/M0+, the vector table size is reduced with up to 32 vectors occupying 0x80 bytes.
The vector table can be placed in read-only memory or RAM. Placing it in ROM saves RAM space while locating it in RAM allows dynamic updating of vector addresses. The VTOR register controls the starting address of the vector table. On reset, the processor loads the VTOR with the start address of the vector table which is typically 0x00000000 in flash memory. The processor fetches the initial stack pointer and exception vectors from this VTOR-defined vector table base address.
VTOR Register Details
The VTOR register is a 32-bit writeable CPU register present in all Cortex-M variants. It specifies a byte-aligned offset which gets added to the vector table base address defined in the system memory map. This provides the actual start address of the vector table. The VTOR offset can be changed dynamically to relocate the vector table.
The VTOR supports alias addresses 0xE000ED08, 0xE000ED0C and 0xE000ED10. Writing to any of these addresses updates the VTOR value. On reset, the processor loads the VTOR with the fixed vector table base address which is 0x00000000 for Cortex-M0/M0+ and 0x00000004 for Cortex-M3/M4. This maps the vector table to the start of the code memory region.
Bit[8:0] of the VTOR hold the offset value added to the vector table base address. The upper bits [31:9] are reserved. The offset can specify a 4KB aligned address range for the vector table anywhere in the 4GB memory space.
Relocating Vector Table using VTOR
Modifying the VTOR allows flexible positioning of the vector table in processor memory space. It can be moved to RAM for dynamic vector entries. Or it can be placed in read-only memory to save RAM space. Let’s look at how VTOR can relocate the vector table:
1. Vector Table in Flash Memory (Default)
By default, the vector table resides at the start of flash memory in the Cortex-M memory map. For this default mapping:
- VTOR holds the flash base address (0x00000000 for M0/M0+, 0x00000004 for M3/M4).
- No offset added to the base address.
- Vector table positioned at the start of flash.
2. Vector Table Relocated to RAM
The VTOR can be programmed to relocate the vector table to RAM. For example:
- MAP RAM to address 0x20000000 in memory map
- Set VTOR to 0x20000000
- Offset of 0x20000000 added to flash base address
- Vector table now positioned at start of RAM
This allows dynamic modification of exception vectors.
3. Vector Table in ROM
To save RAM space, the vector table can also be placed in ROM via VTOR:
- MAP ROM to address 0x10000000
- Configure VTOR to 0x10000000
- 0x10000000 offset added to flash base
- Vector table located in ROM saving RAM.
VTOR Configuration in Cortex-M
The VTOR register can be configured and modified in different ways:
- Startup code: The VTOR is typically configured in the processor startup code based on the memory map.
- CMSIS functions: The CMSIS core header files provide API functions to set the VTOR value at runtime.
- Direct access: VTOR can be directly written to in code via its alias addresses.
- Debug probe: The VTOR can be modified via the debug interface using a debug probe.
This enables flexible positioning of the vector table by altering the VTOR dynamically as required.
Using VTOR to Configure Vector Table Location
Here is an example demonstrating how VTOR can be used to configure the vector table location in Cortex-M:
1. Default Vector Table in Flash
/* Flash memory starts at 0x08000000 */ /* Default vector table positioned at start of flash */ VTOR = 0x00000000; /* Exception vectors point to ISRs in flash */ Vector = *((volatile uint32_t *)(VTOR + 0x00)); /* Reset ISR */ Vector = *((volatile uint32_t *)(VTOR + 0x04)); /* NMI ISR */ …..
2. Relocated Vector Table in RAM
/* MAP RAM at 0x20000000 */ /* Relocate vector table to RAM */ VTOR = 0x20000000; /* Vectors now point to ISRs in RAM */ Vector = *((volatile uint32_t *)(VTOR + 0x00)); /* Reset ISR */ Vector = *((volatile uint32_t *)(VTOR + 0x04)); /* NMI ISR */ …..
This demonstrates VTOR’s ability to remap the vector table location in Cortex-M flash to RAM or ROM.
Advantages of VTOR Relocation
Key benefits of using VTOR to relocate the vector table include:
- Position vector table in RAM for dynamic vector entries
- Locate vector table in ROM to conserve RAM usage
- Update vector addresses by modifying VTOR at runtime
- Customize vector table placement for different applications
- Provide flexibility in vector table memory mapping
- Enable table placement in memory optimal for performance
Use Cases for VTOR Relocation
Some examples where modifying VTOR to relocate the vector table is useful:
- Bootloaders: Position vector table in ROM separate from application area.
- OS kernels: Move table to RAM for context switching between processes.
- No-OS applications: Locate table in RAM for high-speed ISR switching.
- Memory-constrained devices: Place table in ROM to conserve RAM.
- Security apps: Isolate vector table from rest of code for protection.
Overall, intelligent VTOR configuration provides great flexibility in Cortex-M vector table placement to optimize performance, memory usage, and security.