The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. The Cortex-M cores are designed for microcontroller use, and consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55 and Cortex-M85/M85+ cores. They aim to provide a low-cost platform while having better performance than classic 8-bit and 16-bit microcontrollers.
These ARM Cortex M cores contain common sets of registers that programmers need to understand in order to effectively develop software for devices using Cortex M processors. Let’s take a look at some of the key registers found in Cortex M cores.
Program Status Registers
The Program Status Register (PSR) contains status information about the current state of the processor. This includes flags like the interrupt enable status, execution state bits, and interrupt flags. There are two PSR registers – the Application PSR which is used by application code, and the Execution PSR used by exception handlers. Some key bits include:
- N – Negative condition flag
- Z – Zero condition flag
- C – Carry condition flag
- V – Overflow condition flag
- T – Thumb execution state bit
- I – IRQ interrupt disable bit
- F – FIQ interrupt disable bit
The PSR registers can be accessed using MRS and MSR instructions to move their contents to and from general purpose registers.
Control Registers
The Control registers configure core functionality like memory access, interrupts and exceptions. These include:
- SysTick Control and Status Register – Configures the SysTick timer module
- NVIC ISERx – Interrupt Set Enable Registers to enable interrupts
- NVIC ICERx – Interrupt Clear Enable Registers to disable interrupts
- NVIC ISPRx – Interrupt Set Pending Registers to force interrupts
- NVIC ICPRx – Interrupt Clear Pending Registers to remove pending interrupts
- MPU Type Register – Indicates MPU support level
- MPU Control Register – Controls MPU enable and memory access behavior
- MPU Region Number Register – Specifies current MPU region
- MPU Region Base Address Register – Base address of current MPU region
- MPU Region Attribute and Size Registers – Access controls for MPU region
These control registers allow developers to configure the microcontroller for their specific application requirements.
System Registers
System registers provide core information like the architecture version and clock speeds. These include:
- CPUID – CPU ID register with architecture version info
- ICSR – Interrupt Control and State Register
- VTOR – Vector Table Offset Register to relocate vector table
- AIRCR – Application Interrupt/Reset Control Register
- SCR – System Control Register
- CCR – Configuration and Control Register
- SHPR1-3 – System Handler Priority Registers
- SHCSR – System Handler Control and State Register
- DFSR – Debug Fault Status Register
The system registers allow the core to be configured and provide visibility into current processor state information.
General Purpose Registers
The general purpose registers are used for standard arithmetic and data processing operations. In Cortex M cores these include:
- R0-R12 – General purpose registers for main processor modes
- R13 – Stack pointer register
- R14 – Link register for function calls
- R15 – Program counter
- xPSR – Combined program status register
The general purpose registers provide fast access for time critical code execution in the core. Having registers directly available avoids slow main memory accesses.
Floating Point Registers
Cortex M4 and M7 cores optionally support single precision floating point with these registers:
- S0-S31 – Floating point registers
- FPSCR – Floating point status and control register
The floating point registers give access to math co-processing capabilities to accelerate algorithms using floating point arithmetic.
Debug Registers
For debugging and understanding program flow and processor state, Cortex M cores include:
- DHCSR – Debug halt control and status register
- DCRSR – Debug core register selector register
- DCRDR – Debug core register data register
- DEMCR – Debug exception and monitor control register
Through the debug registers and the Debug Access Port (DAP) on Cortex M chips, external debuggers can halt execution, access registers and memory, set breakpoints, and trace instruction execution.
Summary
In summary, ARM Cortex M cores contain a standardized set of registers to control the core, enable advanced functionality like memory protection, service interrupts, provide debugging capability, and perform general purpose data processing. Key register types include the program status, control, system, general purpose, floating point, and debug registers. Understanding these registers is essential for both firmware engineers developing products with Cortex M and software engineers looking to optimize code.
