Cortex-M3 microcontrollers feature a flexible reset sequence that allows system designers to customize the reset process to meet their specific needs. The reset sequence controls the initial boot process and determines how the processor initializes itself after reset. Understanding the default reset sequence and the available configuration options is key to properly initializing the Cortex-M3 system.
Default Reset Sequence
After the reset pin is deactivated, the Cortex-M3 microcontroller goes through the following default reset sequence:
- Processor is held in reset state
- Reset clock starts on-chip oscillator
- Power-on reset occurs to initialize critical registers
- Clock generation circuitry initialized
- Memory protection unit configured
- Stack pointer initialized
- Vector table fetched from boot memory
- Processor released from reset state
- Boot process starts executing from reset vector
During the reset sequence, the processor is held inactive while the power, clocks, and memories undergo initialization. The reset handling circuitry controls this process independently of the core processor logic. Once the memories, clocks, and hardware blocks are initialized, the processor is released from reset and starts executing boot code from the vector table.
The first part of the reset sequence is power-on reset (POR). This initializes critical registers inside the processor to default values for basic operation. POR configures the following:
- Processor mode set to Thread mode
- Main stack pointer initialized
- Vector table base address register cleared
- System timers, watchdog timers reset
- Processor debug block reset
- Interrupt controller reset
- Processor execution unit reset
After POR, the processor core can start fetching instructions and data from memory. But clocks, memory, and peripherals still need initialization.
The on-chip oscillator starts running from the reset clock during the early part of reset. This oscillator clocks the phase-locked loop (PLL) and clock generation blocks to synthesize the final processor clock frequency. The clock generation hardware supports multiple clock options like internal RC oscillators, external oscillators, and PLLs. The reset sequence initializes the dividers, muxes, PLL, and other clock blocks to generate a stable clock for the processor core and peripherals.
Memory Protection Unit
The Memory Protection Unit (MPU) secures critical code and data regions in memory from access violations. The MPU defines up to 8 protected memory regions and their permissions. The reset sequence configures the MPU regions based on the system security policy. Enabling and properly configuring the MPU is crucial for secure Cortex-M3 operation.
Stack Pointer Initialization
After reset, the Cortex-M3 CPU requires a valid stack pointer to start pushing data during exception entries. The reset sequence initializes the main stack pointer (MSP) to point to a defined area of SRAM for this purpose. The MSP provides the stack space for Thread mode exception handling.
Vector Table Fetch
The final step is fetching the address of the vector table from the Vector Table Offset Register (VTOR). The vector table defines the reset handler and exception handler entry points. The CPU fetches the address of this vector table and starts executing code from the reset handler located at offset 0x00.
Customizing the Reset Sequence
System designers can customize parts of the Cortex-M3 reset sequence to match their system requirements:
- Custom reset handler location
- Initialization of global variables
- Early peripheral initialization
- Custom default stack pointer value
- Multiple stacks for different processor modes
Custom Reset Handler Location
The processor starts executing the reset handler located at the start of the vector table after reset. This location can be customized by changing the vector table offset value in the VTOR register. The custom vector table can point the reset handler anywhere in code memory.
Initializing Global Variables
Uninitialized global variables will have undefined values after reset which can cause issues. The reset handler provides a place to add initialization code for clearing or setting critical global variables.
Early Peripheral Initialization
Some peripherals like memory controllers may require initialization before executing main(). The reset handler allows this early init code to be executed before jumping to the C application entry point.
Custom Stack Pointer
The default stack pointer location may not work for all applications. Changing the stack pointer init value allows using a custom SRAM location for the stack. This value can be changed directly in the VTOR register.
Multiple Stack Pointers
Thread mode uses the MSP while Handler mode uses MSP or PSP depending on context. Having separate stack pointers allows flexibility in stack allocation for different processor modes.
Cortex-M3 Reset Sources
The Cortex-M3 processor supports multiple sources that can trigger a reset sequence. These include:
- Power-on reset
- External system reset
- Watchdog reset
- Software initiated reset
- JTAG reset
Power-on reset (POR) occurs any time the processor powers up after the power supply ramps up. POR provides a controlled reset after power fluctuations or cycling power.
External System Reset
Activating the external reset pin initiates a full system reset. This allows other devices or circuits to reset the Cortex-M3 with a reset button or logic signal.
The watchdog timer resets the system if the processor fails to refresh the timer regularly. This provides automated recovery from software hangs or crashes.
Software Initiated Reset
The Cortex-M3 can reset itself by setting the SYSRESETREQ bit in the Application Interrupt and Reset Control register. This allows the running software to reset the system.
Connecting the Cortex-M3 JTAG interface asserts a JTAG reset signal to the core. This facilitates debugging reset.
Reset Handling Hardware
Dedicated hardware modules control the automated reset sequence. These modules include:
- Reset state machine
- Reset clock control
- Reset status registers
- Clock control registers
- Reset handler memory
Reset State Machine
The reset state machine controls the processor reset inputs and sequences the timing of reset events. State transitions depend on reset signals, clock statuses, and power monitoring.
Reset Clock Control
Generating reliable clocks requires first using slow frequency clocks from on-chip oscillators. The reset clock muxes control the source and enables clocking during the reset sequence.
Reset Status Registers
Status registers like the Reset Status Register provide visibility into the reset state machine. Software can check the reset source and status bits after boot.
Clock Control Registers
These registers control clocking parameters like oscillator frequency, PLL multipliers and dividers, and clock muxing. The registers initialize the clocks for the system.
Reset Handler Memory
Dedicated memory containing the initial bootloader code holds the reset handler and vector table which executes after reset.
Cortex-M3 Register Initialization
The Cortex-M3 reset sequence initializes the following key registers to safe default values:
- Main stack pointer
- Vector table base address register
- Interrupt control registers
- Processor core registers
- Memory Protection Unit registers
- Debug register unlocked for access
- Timer registers reset
- Watchdog registers reset
Main Stack Pointer (MSP)
The MSP provides the primary stack for thread mode. Initializing to a known good value prevents stack corruption.
Vector Table Offset (VTOR)
The VTOR provides the vector table address which contains the reset handler address. This initializes before releasing reset.
Interrupt Control Registers
The interrupt controller registers get initialized to disable interrupts globally during reset. This prevents errant interrupts during boot.
Processor Core Registers
General purpose register R0-R12 are cleared to 0. Initializing these removes uncertainty about register contents.
The MPU registers which control memory access permissions initialize to a known unlocked state during reset.
The debug register gets unlocked allowing debug access after reset. This enables debug visibility after boot.
System timer registers initialize to 0, clearing any pending interrupts and overflow conditions.
Watchdog registers reset, preventing any unexpected watchdog behavior before boot.
Reset Configuration Options
Several configuration options are available to customize reset handling:
- Choosing bootloader memory type
- Selecting reset clock source
- Watchdog timeout period
- Startup delay after reset
- Configuring reset pull devices
- Debug access during reset
Bootloader Memory Type
The bootloader with reset handler can be located in internal flash or external memories like NOR flash.
Reset Clock Source
A low speed internal RC oscillator or external oscillator can provide the initial reset clock. This determines reset duration.
The watchdog timer period before reset expiration can be tuned as needed. Shorter values reset sooner.
Some systems benefit from a pause after reset allowing voltages to stabilize. Delaying reset release accommodates this.
Reset Pull Devices
Configuring embedded resistors or discrete components on reset pins control reset assertion and release timing.
Debug can be enabled or disabled after reset depending on debug needs. Disabling helps security.
Example Cortex-M3 Reset Configuration
Here is an example reset configuration for a Cortex-M3 system:
- Reset handler located in internal flash
- 8MHz internal RC oscillator as reset clock
- 512ms watchdog timeout period
- 100us delay after reset release
- External 10K pull-up resistor on reset pin
- Debug access disabled after reset
This configuration uses the simplicity and reliability of internal oscillators for reset clocking. A 512ms watchdog provides reset recovery without being too aggressive. The 100us startup delay gives I/O voltages time to stabilize. An external pull-up resistor ensures the reset pin asserts cleanly. Debug access is disabled for improved security.
Reset Sequence Timing
The duration of the Cortex-M3 reset sequence depends on the reset clock speed and startup delay configuration. A typical sequence takes hundreds of microseconds:
- 0us – Reset pin asserted
- 10us – On-chip oscillator starts
- 50us – Core registers initialized by POR
- 100us – Clocks initialized from oscillator
- 150us – Vector fetch and stack setup
- 200us – Processor released from reset
The reset clock oscillator determines the minimum reset duration. Slower oscillator frequencies extend the sequence. Reset deassertion depends on the configured startup delay.
Leveraging Reset Flexibility
Cortex-M3 reset configuration options provide design flexibility:
- Stable clocks derived from internal oscillators
- Custom bootloader in any memory type
- Tuned watchdog reset period
- Optimized reset pin control
- Selective debug access
Together these capabilities allow tailoring reset handling precisely for needs:
- Recovery from faulty code states
- Reliable processor initialization
- Transition to application code
- System security enablement
Understanding the default reset behavior and configuration options allows leveraging the Cortex-M3 flexibility for optimized reset handling.
In summary, the Cortex-M3 microcontroller reset sequence initializes the processor and memories for reliable startup. The reset control hardware manages power-on reset, clock stabilization, register configuration, and vector table fetch independent of the core logic. Multiple reset sources provide robust recovery capability. Designers can customize the reset handler location, stack pointers, and other options for their specific application requirements. Configuring reset handling lays the foundation for stable Cortex-M3 startup and execution.