The Cortex-M3 processor offers various low power modes to reduce power consumption during periods of inactivity. By leveraging these low power modes, significant power savings can be achieved in energy-constrained applications such as battery-powered devices.
Sleep mode is the lowest power mode in the Cortex-M3 architecture. In this mode, the core, deep sleep and on-chip memories are powered off. The processor immediately exits sleep mode when an interrupt or reset occurs. Sleep mode reduces power consumption to less than 50% of run mode power.
To enter sleep mode, the WFI (Wait For Interrupt) instruction must be executed. This inserts the processor into a low power state until woken by an interrupt. All processor registers and states are preserved in this mode. Wake up time from sleep mode is around 10 clock cycles.
Deep Sleep Mode
Deep sleep mode offers lower power savings compared to sleep mode. In this mode, the on-chip RAMs and registers lose power and state. The processor is woken by a reset instead of an interrupt in this mode. Wake up time is longer in deep sleep around 100 clock cycles.
To enter deep sleep mode, the WFI instruction must be executed with the DEEPSLEEP bit set in the System Control Register. This powers down more core logic blocks leading to lower power consumption. All RAM contents are lost in this mode. The wake up process restores stack pointers and resets core peripherals from their powered down state.
Power Down Mode
Power down mode achieves the lowest power consumption in the Cortex-M3 architecture. In addition to the RAMs, registers and core logic, the I/O pins and peripherals also lose power and state. Only the External Bus Interface unit remains powered to support low frequency clocks.
To enter power down mode, the WFI instruction must be executed with the DEEPSLEEP and SLEEPDEEP bits set in the SCR register. This maximizes power savings by powering down all unnecessary logic. The wake up time is around 2ms which is substantially higher compared to other low power modes.
Configuring Low Power Modes
Several steps are involved in configuring the Cortex-M3 processor for low power modes:
- Enable selected low power mode by setting the corresponding bits in the System Control Register (SCR).
- Configure wake up sources by enabling interrupts or external triggers like GPIO pins.
- Configure low power peripherals settings such as clocks, dividers and stops.
- Execute the WFI instruction to enter low power state.
It is important to ensure all wake up sources are deactivated before entering low power modes. Failing to do so will prevent the processor from resuming operation.
System Control Register
The SCR register controls entry into low power modes in the Cortex-M3 architecture. This register has the following bitfields related to power modes:
- SEVONPEND – Send Event on Pending bit
- SLEEPDEEP – Controls deep sleep vs sleep mode
- SLEEPEXIT – Sleep Exit bit
- DEEPSLEEP – Controls power down vs deep sleep mode
Setting SLEEPDEEP and DEEPSLEEP bits enables deeper power savings. The SLEEPEXIT bit generates an internal event to wake up the processor. The SEVONPEND bit issues an event when waking up from an interrupt that was pending while in a low power mode.
Wake Up Sources
To resume normal operation from low power modes, wake up sources must be configured appropriately:
- Interrupts – Enabled interrupts from peripherals will wake processor on detecting events
- GPIO Pins – External triggers from pins can wake up processor
- Reset – Activation of external reset or internal wake up resets processor
- Debug – Debug/trace interface can wake processor for debugging
Interrupts are the most commonly used wake up source. Time critical tasks may use GPIO pins as wake up triggers to avoid interrupt latency overhead.
Since peripherals lose state and power in low power modes, their configuration must be saved and restored appropriately:
- Save peripheral state before entering low power if needed for recovery
- Disable peripherals clocks and power domains to maximize power saving
- Configure peripherals to issue interrupts or triggers to wake processor
- Restore peripheral state on wake up before restarting operation
Failing to configure peripherals properly can prevent successful entry and exit from low power modes.
Optimizing for Low Power
Beyond the hardware low power modes, software optimizations can also help reduce power consumption:
- Minimize unnecessary clocks and logic
- Reduce CPU activity and use sleep modes whenever possible
- Choose low power peripheral options like DMA, SPI, I2C
- Minimize memory accesses which consume power
- Use optimal software architecture to maximize sleep time
An efficient mix of hardware low power modes and software optimization delivers the best energy savings in Cortex-M3 applications.
Debugging Low Power Modes
Debugging issues with low power modes requires specialized techniques:
- Ensure wake up sources are configured correctly and enabled
- Verify peripherals are disabling clocks/power and issuing interrupts properly
- Check SCR configuration bits are set appropriately before WFI
- Analyze stack and peripheral state before and after low power mode entry
- Use debugger to step through WFI sequence and verify mode entry
- Monitor key registers and logic with oscilloscope to detect powerdown
A common issue is failing peripherals preventing low power mode from activating due to pending clocks or interrupts. Meticulous testing is required to isolate and fix such issues.
Here are some common use cases for leveraging low power modes in Cortex-M3 designs:
For battery-powered devices like wearables, wireless sensors, remotes etc, the Cortex-M3 low power modes can significantly extend battery life by reducing average power consumption during inactive periods. Sleep and deep sleep modes work well for intermittent events. Power down mode applies for long inactivity between sensor sampling or RF communications.
In energy harvesting applications using solar, vibration, thermal sources etc, the Cortex-M3 low power modes enable operating with very limited power budgets. The processor can remain in sleep mode until sufficient energy is harvested to perform useful work. Deep sleep and power down modes maximize energy savings in resource constrained energy harvesting applications.
Real Time Systems
Sleep and deep sleep modes allow real time systems to reduce power while meeting timing deadlines. By quickly waking up on external triggers or timed interrupts, critical tasks can be run while saving power during inactive periods. This optimizes overall system power while still maintaining determinism.
In summary, leveraging the sleep, deep sleep and power down low power modes available in the Cortex-M3 processor enables significant power savings in various energy-constrained applications. When combined with software level optimizations, these low power capabilities allow Cortex-M3 based systems to operate reliably under tight power budgets.