The Handler mode in Arm Cortex M3 is one of the processor modes that determines the execution privilege level and access rights to system resources. The Cortex-M3 processor has multiple modes to provide protection and safe execution of code. The Handler mode is used to execute exception handlers when exceptions occur during program execution.
When an exception occurs, the processor enters the Handler mode, saves context to stack, and starts executing the exception handler routine. This allows the exception handler to run safely without interference from the code that triggered the exception. Once the exception handler finishes execution, the processor restores the context and returns to the original execution mode before the exception occurred.
Overview of Arm Cortex M3 Processor Modes
The Arm Cortex M3 is based on the Armv7-M architecture and has multiple processor modes with different privilege levels:
- Thread mode – Used to execute main application code with lowest privilege level. This is the default execution mode.
- Handler mode – Used to execute exception handlers with higher privilege than thread mode.
- Privileged Thread mode – Optional mode with higher privilege than thread mode but lower than handler mode. Not used in all Cortex M3 implementations.
- Privileged Handler mode – Optional mode with highest privilege level. Used for critical exception handlers.
The handler and privileged handler modes are designed to execute exception handling routines and have access privileges to fault status registers and other system resources not available in thread mode. This prevents application code from accidentally modifying protected system resources.
Key Features of Handler Mode
Here are some of the key features of the Cortex M3 Handler mode:
- Executes exception handler routines for system exceptions like memory faults, Divide by 0, NMI interrupts etc.
- Has higher privilege level than Thread mode but lower than Privileged modes.
- Can access MSP stack pointer for stack usage during exception handling.
- Can access additional CPU registers like IPSR, Control, Fault Mask and Fault Status registers.
- Allows atomic access to Base Priority Mask register.
- Allows write access to Software Trigger Interrupt register to trigger interrupts.
- Allows access to Debug Halting Control and Debug Core registers.
These additional privileges help the handler mode exception routines to identify the source of exception, handle fault conditions safely, interact with OS kernel for scheduling decisions, trigger interrupts and debug halted core state when required.
How Processor Transitions into Handler Mode
The Cortex M3 processor automatically transitions into Handler mode when any of the following exceptions occur during code execution in Thread mode:
- Memory management exceptions like memory faults, MPU violations etc.
- Bus faults during instruction fetches or data accesses.
- Usage faults due to divide by 0, invalid state etc.
- Supervisor calls to OS kernel for privilege tasks.
- Debug monitor exceptions when debug is enabled.
- PendSV and SysTick exceptions used for OS task scheduling.
The processor pushes context like program counter, registers etc. to stack and loads the exception handler address from the vector table. The first instruction in the target handler routine is executed in Handler mode with higher privilege. This context switching is done automatically in hardware.
Privileged Access in Handler Mode
The Handler mode allows privileged access to the following CPU registers and resources not available to Thread mode:
- Special CPU Registers: IPSR, APSR, EPSR
- System Control Registers: CONTROL, FAULTMASK, BASEPRI
- Memory Management/Bus Fault Status Registers
- Debug Halting Registers and Debug Monitor Access
- Access to MSP stack pointer for Handler stack
- Atomic access to BASEPRI register to set interrupt masking priority
- Can trigger PendSV and SysTick exceptions for scheduling
This privileged access enables the handler mode code to identify the source of exception, save status for crashes, interact with OS kernel, change interrupt priority masking and debug halted system efficiently.
Typical Uses of Handler Mode
Here are some typical use cases where Cortex M3 enters Handler mode to execute exception routines:
- Memory Faults – On invalid memory access errors, HardFault handler is called in Handler mode to log and handle the fault.
- Divide by Zero – On a Divide by Zero exception, the handler is called in Handler mode to return error status safely back to application.
- OS Scheduling – PendSV handler invoked in Handler mode to implement context switching and scheduling by OS kernel.
- Supervisor Call – Application calls SVC instruction to execute privileged tasks in SVC handler safely.
- Debug Monitor – Monitor handler entered on debug events to allow inspection of system state during debugging.
Registers Available in Handler Mode
The following CPU registers are available for the exception handler to use in Handler mode:
- General purpose registers R0-R12
- Stack pointer registers MSP, PSP
- Link register LR to store return address
- Program counter PC for instruction address
- Application Program Status Register APSR
- Exception Return Value EXC_RETURN
- Priority Mask BASEPRI register
- Interrupt Program Status Register IPSR
The MSP stack pointer is commonly used in Handler mode for pushing register context during exception entry and popping during exception return. The IPSR helps identify the exception number that triggered entry into Handler mode.
Returning from Handler Mode
To return from Handler mode back to original execution mode, the handler does the following steps:
- Optionally write EXC_RETURN value to specify Thread or Privileged mode return
- Pop saved context from stack to restore register values
- Execute exception return instruction to exit handler
The EXC_RETURN value instructs the processor which execution mode to return to after exception handling is done. The BX LR instruction is commonly used to exit the handler and resume original execution.
Privileged Thread Mode vs Handler Mode
In Cortex M3 implementations that include an optional Privileged Thread mode, the Handler and Privileged Thread modes have the following differences:
- Handler mode has higher priority than Privileged Thread mode
- Handler routines run on MSP stack while PSP used for Privileged Threads
- Some CPU registers like IPSR available only in Handler mode
- Atomic BASEPRI access allowed only in Handler mode
So while Privileged Threads have higher privilege than Thread mode, the Handler mode has additional access permissions required for exception handling. The Privileged Thread mode is not widely used in Cortex M3 designs.
To summarize, the key points about Arm Cortex M3 Handler mode are:
- Executes exception handler routines when exceptions occur in Thread mode
- Has higher privilege access than Thread mode for managing exceptions
- Automatically entered by hardware on exceptions and interrupts
- Accesses additional registers and resources not available in Thread mode
- Stack pointer switched from PSP to MSP on handler entry
- Used for critical system exceptions like memory faults, divide by zero etc.
- Returns to original execution mode after handling exception
The privileged Handler mode enables robust and safe exception processing in Cortex M3 applications. Understanding its capabilities allows developers to write efficient exception handlers leveraging the architecture features.