What is the difference between link register and stack pointer?

The link register and stack pointer are two important registers used for different purposes in ARM Cortex processors. The main differences between the two can be summarized as:

• The link register (LR) stores the return address when a function call is made. It allows a program to return to the instruction after a function call completes.
• The stack pointer (SP) points to the top of the stack in memory. It is used to allocate and deallocate stack space for function calls.
• The LR is loaded with the return address when BL/BLX (branch with link) instructions are executed. The SP is updated by push and pop instructions.
• The LR is a general purpose register R14. The SP is register R13.
• The LR is part of the ARM Procedure Call Standard used for subroutine calls and returns. The SP is used for general stack operations.
• The LR contents depend on program flow. The SP follows a mostly sequential pattern.
• The LR works closely with the PC (program counter). The SP works closely with data processing and memory access instructions.
• The LR is banked – each exception mode has its own copy. The SP is banked between some but not all modes.

To summarize, the link register handles return addresses for function calls while the stack pointer handles allocation/deallocation of stack memory during program execution. The LR is associated with branches/subroutines while the SP is associated with sequential stack operations.

Link Register in More Detail

The link register (LR) is register 14 in ARM Cortex processors. Its primary purpose is to store the return address when a branch with link instruction such as BL or BLX is executed. These branch with link instructions store the address of the next instruction (return address) in the LR register before changing the program counter to branch.

Some key points about the link register:

• It allows subroutines and functions to quickly store the return address so they can return after completing their task.
• It is declared as a general purpose register in ARM procedure call standard.
• In Cortex-M profiles, the LR is accessible as register R14 in the ARM register naming convention.
• In Cortex-A profiles, it is accessible as X30 in ARM64 register naming convention.
• The LR is banked across exception modes – each mode has its own copy.
• This allows the return address for each mode to be stored separately.
• In privileged modes, LR is called the exception return link register.
• LR is closely associated with the program counter (PC) to handle subroutine returns.

Overall, the link register handles the critical role of storing return addresses during branch and link operations so that subroutines can quickly return to the calling code.

Stack Pointer in More Detail

The stack pointer (SP) is register 13 in ARM Cortex processors. Its main purpose is to point to the top of the stack frame in memory. The value of the SP changes as data is pushed to and popped from the stack.

Some key points about the stack pointer:

• It indicates the current end of the stack in memory where the next data would be stored.
• It is declared as a general purpose register by the ARM architecture.
• In Cortex-M, it is accessible as R13. In Cortex-A, it is accessible as X31.
• The SP is banked between some but not all processor modes.
• Updating the SP value grows or shrinks the current stack frame.
• PUSH and POP instructions manipulate the stack pointer.
• It works very closely with memory access instructions.
• The SP enables key stack operations like local variable allocation.

In summary, the stack pointer tracks the top of the stack as functions allocate and deallocate stack memory for local variables and other stack data. It plays a key role in sequential stack operations.

Typical Usage Examples

Here are some examples that demonstrate the typical usage of the link register and stack pointer:

Link Register Usage

• Storing return address before function call: BL function_name
• Reading LR to get return address: MOV R0, LR
• Restoring return address from LR: BX LR
• Pushing LR to save return address: PUSH {LR}

Stack Pointer Usage

• Allocating stack space for local variables: SUB SP, SP, #12
• Pushing registers onto stack: PUSH {R4-R8}
• Popping stack contents back to registers: POP {R4-R7}
• Freeing stack space: ADD SP, SP, #12

These examples show how the LR is closely associated with branches while the SP is associated with sequential stack allocation, access, and deallocation.

Differences in Processor Modes

The link register and stack pointer also differ in their behavior across processor modes:

• The LR is banked – each processor mode has its own LR register.
• The SP is partially banked – some modes share a single SP.
• Inprivileged Thread modes share the same SP.
• In Cortex-M, Handler and Thread modes bank SP.
• In Cortex-A, all modes have separate banked SP registers.

This banking enables the separation of stack memory between different processor modes as needed. The LR banked nature also allows thread-independent return addresses.

Interaction with BLX Instructions

The BLX instruction demonstrates the interplay between the LR and PC registers:

1. BLX does branch with link, storing return address in LR
2. BLX can change instruction set, altering bottom bits of PC
3. Return address in LR maintains proper PC value for return
4. BX LR restores full PC value from LR to return

So BLX relies on the LR to store a complete, mode-specific return address to allow seamless subroutine returns.

Stack Frame Organization

The stack pointer tracks the organization of data within a stack frame. A typical stack frame with local variables and saved registers would store data like: [SP] => Local Var 1 [SP+4] => Local Var 2 [SP+8] => Saved FP [SP+12] => Saved LR [SP+16] => Saved R4 [SP+20] => Saved R5

Here the stack pointer marks the top of the stack. It is incremented as data is pushed and decremented as data is popped. Managing this stack data organization is a key SP role.

Interrupt and Context Switching

During interrupts and context switches:

• SP must be banked/saved/restored to maintain separate stack frames.
• LR must be banked/saved/restored to retain return address.

This allows the interrupt handler to allocate stack space without corrupting the interrupted program’s call stack.

OS/Context Switch Usage

For operating system context switching:

• SP and LR are saved to the Process Control Block.
• This allows restoring the process stack frame when switching back.

The LR and SP registers are key to preserving the execution state across context switches.

Enter and Exit Hooks

In functions performing context switches:

• Registers can be automatically saved/restored at function entry and exit points.
• Prolog/epilog code handles this by pushing LR, FP, and other registers.

This provides transparency during context switches and interrupts to maintain proper stack frames.

Summary

In summary:

• The link register handles return addresses for subroutines and functions.
• The stack pointer handles stack allocation and access.
• The LR works with branches while the SP works with sequential stack ops.
• The LR and SP must both be preserved across interrupts and context switches.
• Understanding their differences allows robust subroutine calls and stack management.

The link register and stack pointer have distinct but complementary roles in ARM Cortex processors to support critical operations like branches, subroutine calls, interrupts, and context switching. Both registers are essential to understand for robust assembly and C programming on ARM platforms.