The ARM Cortex-M series is a range of 32-bit RISC ARM processor cores licensed by Arm Holdings. Cortex-M cores are designed for low-cost and low-power embedded applications such as microcontrollers, automotive body systems, IoT devices, home appliances etc. The Cortex-M series focuses on ease of use, small silicon footprint, low power consumption, and low cost while delivering good performance.
Overview of ARM Cortex-M Series Architecture
The Cortex-M series architecture is based on the ARMv6-M, ARMv7-M, and ARMv8-M architectures. The key features of Cortex-M cores include:
- 32-bit RISC instruction set with Thumb-2 technology for improved code density
- Advanced single cycle datapath and constant bus latency for deterministic execution timing
- NVIC (Nested Vectored Interrupt Controller) for fast and deterministic interrupt handling
- Integrated sleep modes and low power design for energy efficiency
- Memory Protection Unit (MPU) for software-based memory protection
- Tightly-coupled memory support for deterministic high performance execution
- DSP instructions for digital signal processing applications
- Optional Floating Point Unit (FPU) for single and double precision operations
- Debug and trace support for simplified software debugging
The Cortex-M series is divided into three architectural profiles – Cortex-M0/M0+ profile aimed at deeply embedded applications, Cortex-M3/M4/M7 profile for advanced microcontroller applications, and Cortex-M23/M33 profile for embedded applications requiring digital signal processing and high-performance machine learning.
The ARMv6-M architecture introduced the Cortex-M0/M0+ profile to meet the needs of deeply embedded applications like sensors, wearables, etc. It is a stripped down version of the ARMv7-M architecture focused on minimizing silicon area and power consumption. The key features of ARMv6-M architecture are:
- Supports Thumb-2 instruction set with 16-bit and 32-bit instructions for code density
- Supports only 32-bit data types unlike mixed 16/32-bit data types in ARMv7-M
- 2-stage pipeline compared to 3-stage pipeline in ARMv7-M simplifying timing analysis
- Optional MPU with 8 regions compared to 8/16 regions in ARMv7-M
- reduced exception support – only Reset, NMI and HardFault exceptions
- Tail-chaining feature to reduce interrupt latency
- Integrated sleep modes, wait for interrupt/event modes for low power
The Cortex-M0 is the first and smallest core based on ARMv6-M architecture with gate count of 12K gates. It has a 2-stage pipeline, no MPU or FPU, and includes sleep modes, bit-banding and single cycle I/O. The Cortex-M0+ core adds more features like single-cycle multiply, additional SRAM clock cycle, and more efficient branch coding.
ARMv7-M architecture added more features oriented towards microcontroller applications with medium complexity requirements. The key aspects of ARMv7-M architecture are:
- 3-stage pipeline (Fetch, Decode, Execute) for higher performance
- Thumb-2 instruction set with both 16-bit and 32-bit instructions
- Mixed 16-bit and 32-bit data types
- Hardware divide in core for better code efficiency
- Optional FPU support with up to single precision
- MPU with 8 or 16 regions for memory protection
- NVIC for low latency interrupt handling
- More debug features like breakpoint unit, instrumentation trace macrocell, etc.
The Cortex-M3 core was the first implementation of ARMv7-M architecture. With gate count of 23K gates, it delivered significantly higher performance than Cortex-M0/M0+ cores. Key features include digital signal processing (DSP) instructions, optional memory protection unit (MPU), low power modes, and optional FPU. The Cortex-M4 builds on M3 with additional DSP instructions and optional floating point unit (FPU) for signal processing. The Cortex-M7 is highest performance core in ARMv7-M family, aimed at applications requiring high computation and digital signal processing capabilities.
ARMv8-M Architecture and Mainline vs Baseline
ARMv8-M architecture introduced two profiles – Mainline and Baseline for different application requirements. Mainline cores add more features for security, safety, machine learning while baseline cores focused on low cost products.
Mainline ARMv8-M cores include:
- TrustZone for ARMv8-M for security extensions
- MPL extensions for memory protection
- DSP extensions for digital signal processing
- Optional FPU with single and double precision
Baseline ARMv8-M cores include:
- Minimal changes from ARMv6-M/ARMv7-M for easy migration
- Optional MPU for memory protection
- DSP instructions for enhanced DSP performance
- FPU optional in Cortex-M23 core
The Cortex-M23 is first Baseline ARMv8-M core with similar features as Cortex-M3. The Cortex-M33 brings Mainline features like TrustZone, DSP and FPU targeted at applications like industrial IoT, voice recognition, motor control etc. requiring higher performance.
ARM Cortex-M Instruction Set Architecture
The Cortex-M series uses the Thumb instruction set derived from ARM architecture. Thumb-2 extends the original Thumb ISA with additional 32-bit instructions while retaining the 16-bit Thumb instructions. This provides a good balance of high code density with improved performance. Key aspects include:
- Highly optimized for C compilers
- 16-bit and 32-bit instructions for improved code density
- Uniform register file access – all registers accessible from all instructions
- Load/store architecture with most instructions operating on registers
- Simple addressing modes
- Callee-saved registers for fast subroutine calls
- Hardware stack with load/store instructions
- Efficient exception handling and interrupt latency
The instruction set provides support for applications written in C/C++, including integer, bitwise, floating point, and DSP operations. Assembly is rarely needed owing to high code density of Thumb-2 instruction set. The consistent RISC architecture enables building efficient C compilers, simplifies instruction pipelining, and reduces overall system power consumption.
ARM Cortex-M Processor Modes and Exceptions
The Cortex-M series processors support two modes of operation:
- Thread Mode – used for running normal application code. Thread mode has access to all CPU registers.
- Handler Mode – used for handling exceptions and interrupts. Handler mode has access to limited CPU registers for security.
Exceptions supported by Cortex-M processors include:
- Reset – triggered on power up or external reset signal
- NMI – Non maskable interrupt – highest priority interrupt
- HardFault – escalation for all fault conditions
- MemManage – memory protection faults like MPU violations
- BusFault – memory related faults like invalid instruction fetch
- UsageFault – software errors like invalid state, divide by zero
- SVCall – supervisor call using SVC instruction
- DebugMonitor – for debug state entry and exit
- PendSV – pendable request for context switching
- SysTick – system timer for timekeeping and task management
Deterministic interrupt latency and minimal context switching overhead allows Cortex-M cores to respond quickly to external events and support real-time applications efficiently.
ARM Cortex-M Processor Programming Model
The Cortex-M processor programming model is highly optimized for embedded applications written in C/C++ and assembly language. The key aspects are:
- Efficient exception handling for rapid interrupts
- Banked stack pointers for each exception handling mode
- Lazy stacking to minimize context switching time
- Automatic state saving and restoration
- Single cycle digital signal processing instructions
- Bit-banding for atomic bit manipulation
- Deterministic interrupt latency and execution timing
- Wakeup interrupt controller (WIC) for low power mode exit
- Assembler macros for common OS services like context switch
The consistent RISC architecture and Thumb-2 instruction set enables straightforward assembly programming, portable C code, and efficient exception handling – making the Cortex-M family easy to program even for embedded software beginners.
ARM Cortex Microcontroller Software Interface Standard
CMSIS (Cortex Microcontroller Software Interface Standard) defines a common hardware abstraction layer for all Cortex-M processor cores to simplify software reuse across different vendors. It standardizes:
- Processor header files describing the core peripherals
- SVD files describing microcontroller peripherals
- API for RTOS, drivers, middleware
- Debug access using CoreSight components
- Software pack format for software distribution
CMSIS enables device abstraction by providing consistent APIs for core and vendor peripheral access. It allows code reuse across compatible Cortex-M microcontrollers reducing software development effort.
The Cortex-M series offers a range of 32-bit processor cores scalable for various embedded applications. The combination of compact Thumb-2 instruction set, deterministic single cycle execution, fast interrupt handling, integrated debug features, and CMSIS standardization makes the Cortex-M series an ideal choice for embedded microcontroller implementations requiring low cost, low power, ease of development, good performance, and hardware efficiency.