Setting a section’s attributes using the Memory Protection Unit (MPU) can affect the CPU’s ordering of that specific section. The MPU allows configuring access permissions and cache policies for different memory regions. Setting strict ordering for a section via the MPU results in the CPU forcing transactions to that section to occur in program order. This prevents reordering optimizations that could cause problems for self-modifying or tightly coupled driver code.
Overview of Sections and MPU
Sections are independent units of code or data that can be individually configured and mapped into memory. On ARM processors, the MPU allows assigning section-level attributes like:
- Access permissions (read/write/execute)
- Caching policies (cacheable/non-cacheable)
- Memory types (normal, device, strongly ordered)
- Allocation strategies (static, dynamic)
The MPU provides hardware-level isolation and protection for different memory regions. It divides the memory map into a set of sections called MPU regions. Each MPU region can be configured with different attributes. The attributes control things like:
- Which CPU modes can access the region (e.g. user mode vs privileged mode)
- What kind of accesses are allowed (read/write/execute)
- The caching policy for the region
When the CPU generates a memory access, the MPU hardware checks if the access matches the configured attributes of any region. If not, the MPU triggers a fault exception. This prevents potentially dangerous accesses before they reach memory.
MPU Region Ordering and Reordering
One important MPU region attribute is the shareability attribute. This controls the memory ordering applied to that region. The options are:
- Non-shareable – System ordering is applied. Allows reordering for performance.
- Inner Shareable – Inner shareable ordering applied. Some reordering allowed.
- Outer Shareable – Outer shareable ordering applied. Strictest ordering.
- Strongly Ordered – Strongest ordering, no reordering of any kind.
Strongly ordered and outer shareable regions have very strict ordering, forcing all transactions to that region occur in program order. This disables any reordering optimizations by the CPU, memory system, or interconnect.
Non-shareable regions allow the most reordering flexibility. The CPU can reorder transactions to different non-shareable regions. Caches and interconnects can also reorder transactions as long as system correctness is maintained.
MPU Ordering Effects
Setting a section to use strongly ordered or outer shareable attributes via the MPU prevents the CPU and memory system from reordering accesses to that section. Some examples include:
- Self-modifying code sections should use strongly ordered attributes. This ensures instruction fetches get updated data, not stale cached values.
- Memory-mapped peripheral register sections should use strongly ordered attributes. This prevents reordering that could cause race conditions.
- Multiprocessor shared memory sections should use outer shareable attributes. This ensures all CPUs see memory accesses in the same order.
For normal data and code sections, non-shareable attributes can be used. This allows the CPU and caches to aggressively reorder accesses to different non-shareable regions for performance. Reordering works safely as long as dependent accesses use full memory barriers as needed.
Setting Section Attributes with MPU
There are a few common ways to set section attributes using the MPU on ARM processors:
- The MPU driver can configure MPU regions during kernel initialization based on mappings defined in the linker script.
- Hypervisors may configure the MPU to isolate guest OS memory into different regions.
- Some MPUs allow section attributes to be dynamically reconfigured at runtime via MPU driver APIs.
- Higher level APIs like the OS memory protection API can set MPU attributes when creating special memory sections.
For example, to create a strongly ordered shareable memory section, the MPU region would be configured to match the memory address range for that section. The region attributes would be set to permit the required accesses with strongly ordered shareability.
Aligning the MPU regions properly with memory sections prevents accesses from hitting the wrong MPU region. Misalignment could cause unintended faults or reordering for sections.
Effects on Memory Subsystem
The CPU ordering enforced by MPU attributes can influence the broader memory subsystem behavior:
- Non-cacheable attributes bypass caches, eliminating reordering side effects.
- Write-through cacheable attributes prevent reordering writes vs later reads.
- Strongly ordered attributes force interconnect transactions in order.
Conversely, the memory subsystem can limit the MPU’s effects if it reorders transactions across regions. Using strongly ordered attributes ensures strict ordering regardless of the memory system behavior.
The MPU allows assigning memory ordering attributes like strongly ordered and outer shareable to memory regions. Applying such strict ordering to a section via the MPU prevents the CPU and memory system from reordering transactions to that section. This is essential for self-modifying code, memory-mapped peripherals, shared memory, and other critical sections. Careful use of MPU attributes can enable both optimal performance and correct behavior across interacting sections.