The simple answer is yes, the type of memory used – normal or device – can affect system behavior on Cortex M0/M0+ microcontrollers. The key differences between normal and device memory relate to speed, accessibility, and volatility. Understanding these differences allows developers to optimize memory usage for their specific application requirements.
Normal memory refers to standard SRAM or DRAM modules connected externally to the Cortex M0/M0+ microcontroller. This memory resides on the system bus and is generally faster than internal memory. Key characteristics of normal memory include:
- Higher speed – External memory typically runs at a higher clock speed than internal flash or SRAM resulting in lower access times.
- Larger capacity – External memory modules provide more memory capacity, from kilobytes up to megabytes.
- Volatile – Contents are lost when power is removed, requiring rewrite after reset.
- Cached – An optional system cache improves average access time.
- Arbitrated bus access – The microcontroller shares the system bus with other peripherals which can cause wait states.
Device memory refers to internal SRAM and flash modules integrated within the Cortex M0/M0+ chip. This memory has a dedicated connection to the CPU resulting in predictable access times. Key characteristics of device memory include:
- Slower speed – Internal SRAM and flash run at CPU frequency, which is often lower than external memory speed.
- Limited capacity – On-chip memory is restricted, ranging from kilobytes up to low megabytes.
- Non-volatile flash – Contents are retained when power is removed.
- No cache – Access times cannot be improved through caching.
- Dedicated CPU access – No bus arbitration, memory requests go directly to the CPU.
Impact on System Behavior
The differing characteristics of normal and device memory can impact system behavior in the following ways:
The higher speed of normal memory compared to device memory means tasks may complete faster when using external RAM. This is especially noticeable for data-intensive operations like DSP algorithms. However, the lack of caching for device memory provides more predictable response times.
Executing code from slower device flash extends the boot sequence. External memory allows faster boot by fetching code from higher speed NOR flash.
Relying solely on device memory requires rewrite of volatile data after power loss. Normal memory needs backup power to retain contents. Hybrid approaches leverage non-volatile device memory and faster external RAM.
The arbitrated nature of the system bus can create variability in access times for normal memory. Device memory has fixed access latency due to its dedicated CPU connection.
External memory and its supporting bus drivers consume more total power than on-chip memory. Dynamic power varies with interface activity.
Task stacks must fit within available device SRAM, which is limited. Additional normal memory allows larger stack allocations. External memory also enables memory allocation features like malloc/free.
Small on-chip flash limits total application code size. Normal memory allows much larger programs at the cost of external storage.
There are a number of techniques for optimizing normal and device memory usage on Cortex M0/M0+:
- Place performance critical code and data in faster normal memory
- Use device memory for startup, interrupt handlers, and real-time tasks
- Minimize accesses to slower device memory
- Buffer I/O data transfers using normal memory
- Reduce stack usage through static allocation and limiting recursion
- Enable the system cache for normal memory if available
- Use device flash for boot code and read-only data
- Leverage byte addressability of device memory
Proper utilization of both normal and device memory types allows developers to balance performance, reliability, power, and cost when using Cortex M0/M0+ microcontrollers.
In summary, the type of memory used can impact Cortex M0/M0+ system behavior in areas like speed, volatility, determinism, availability, and power consumption. Understanding the key differences between normal and device memory enables developers to make informed design decisions. Optimizing memory usage involves balancing tradeoffs and mapping functionality appropriately based on memory characteristics.