The synthesis and front-end (FE) sign-off process for an ARM Cortex-M0 design involves several key steps. At a high level, these include:
- Setting up the design in the synthesis tool (Synopsys Design Compiler, Cadence RTL Compiler, etc.)
- Synthesizing the RTL to gates
- Analyzing timing, area, power
- Making optimizations and constraints to meet timing, area, power targets
- Generating testbench, testing functionality
- Preparing and reviewing documentation
- Closing timing, area, power sign-off checklists
Let’s look at each of these steps in more detail:
1. Setting Up the Design
The first step is to setup the RTL design files, constraints, scripts, and libraries in the synthesis tool. Some key items here:
- Obtain the RTL code for the Cortex-M0 design from ARM or your internal teams. This will include the register transfer logic (RTL) code for the core logic, interfaces, peripherals, etc.
- Setup a synthesis project and include all the RTL source files.
- Setup the target technology library (standard cell, I/O cells, memories, etc.) provided by the foundry or IP vendor.
- Import any ARM-provided scripts for setting up the design and the ARM Artisan standard cell libraries.
- Setup timing and design constraints. The SDC file will constrain clock frequencies, input/output delays, false paths, multi-cycle paths, etc.
- Set compiler directives and scripts for optimizing the design.
2. Synthesizing the RTL to Gates
Once the setup is complete, we can now synthesize the RTL code down to actual logic gates and cells from the target library. Some key steps here:
- Run logic synthesis to convert RTL to gates. The compiler will infer logic based on the RTL code.
- Optimize for timing, area. This maps logic to optimal standard cell types from the library to meet design goals.
- Iterate synthesis runs with different constraints to try to close timing and area.
- Resolve any issues with unmapped logic or timing QoRs.
3. Analyzing Timing, Area, Power
After synthesis, we need to analyze the results to ensure we have met the Cortex-M0 design goals for timing, area/gate count, and power. This involves:
- Review timing reports – setup slack, hold slack, critical paths, fmax, etc.
- Review area reports – cell area, cell count, instances, macros, etc.
- Review power reports – total power, dynamic, static, by clock domain, etc.
- Compare results vs. ARM-provided goals and iterate as needed.
- Analyze which paths are limiting timing closure.
4. Making Optimizations and Constraints
Based on the analysis in step 3, we need to make optimizations and constraints to meet the Cortex-M0 QoRs.
- Tweak compiler directives to optimize for timing, area, or power as needed.
- Add timing exceptions for false paths to exclude from timing analysis.
- Modify clock constraints to balance skew and uncertainty.
- Restructure the RTL manually if needed for better results.
- Change the target cell library or use different cell drive strengths if timing closure is difficult.
With successive iterations of optimizations and analysis, we aim to meets the ARM-provided constraints for timing, area, and power.
5. Generating Testbench, Testing Functionality
While meeting timing, area, power goals, we also must ensure functional correctness:
- Generate a testbench to stimulate synthesized gate-level netlist.
- Compare outputs versus original RTL testbench to check correctness.
- Debug and fix any functional failures observed.
- Add functional coverage points.
- Achieve test requirements specified by ARM.
Any functional bugs or coverage issues observed need to be debugged, fixed, and re-verified before sign-off.
6. Preparing and Reviewing Documentation
Thorough documentation is critical throughout the project. This includes:
- Timing reports, area reports, power reports for pre-signoff review.
- Scripts, logs, synthesis strategy documentation.
- Tracking sheets for timing exceptions, IO delays, constraints.
- Datasheets, architecture documents from ARM.
- Project schedule, risk assessments, open issues.
Reviews of the documentation ensure nothing is missed for a smooth sign-off process.
7. Closing Timing, Area, Power Sign-off Checklists
The final FE sign-off requires closure of all checklists, including:
- Static timing analysis sign-off – fmax margins, timing exceptions validated, etc.
- Area sign-off – gate count within budget, density acceptable, etc.
- Power sign-off – power within limits, RTL vs. gate correlation done, etc.
- Test and verification sign-off – test plans completed, coverage closure, etc.
- Documentation review sign-off – datasheets, reports, tracking sheets reviewed.
All open items must be closed out, waivers obtained as needed, and management sign-off completed on each checklist. This comprehensive sign-off ensures the Cortex-M0 front-end design is ready to handoff to the back-end implementation teams for layout, physical implementation, timing closure, and tapeout.
In summary, successful synthesis and FE sign-off of an ARM Cortex-M0 requires meticulous setup, constraint development, QoR optimization, functional verification, and documentation closure. When executed well across this 7 step process, it ensures a high quality RTL to GDSII implementation of the Cortex-M0 CPU.