ARM processors are designed to be power-efficient and low-power for use in mobile devices. This allows mobile devices like smartphones and tablets to have good battery life without frequent recharging.
Reduced Instruction Set Computing (RISC)
ARM processors use a RISC architecture which uses simpler instructions that can execute within a single clock cycle. This differs from complex instruction set computing (CISC) used in x86 processors which have complex instructions that may take multiple cycles. The RISC design of ARM reduces power usage.
Pipeline Design
The pipeline in ARM processors is optimized for low power operation. Pipelining allows multiple instructions to be executed in parallel by dividing them into stages. ARM uses techniques like extensive clock gating, operand isolation and write buffers to minimize power in the pipeline.
Clock Speed
ARM processors are designed to operate at relatively low clock speeds compared to x86 chips. Operating at lower frequencies allows significant power savings. ARM cores are optimized to provide full performance at clock speeds of 1-2 GHz which helps reduce the overall power draw.
Power Gating
ARM processors make extensive use of power gating or the ability to cut off power to parts of the chip that are idle. This prevents leakage current from flowing through transistors when they are not switching. Power gating unused sections can reduce power dissipation by up to 90%.
Voltage Scaling
ARM implements dynamic voltage scaling which allows the CPU voltage to be adjusted on the fly based on workload. Operating voltage can be reduced during periods of low activity to save power. Voltage scaling is managed by the processor or the PMIC.
Silicon Process
ARM processor cores are designed to take advantage of smaller transistor geometries like 28nm, 20nm or 14nm. The latest manufacturing processes allow for lower voltage operation and reduced leakage current leading to gains in energy efficiency.
Power Optimization
ARM optimizes power at the circuit level, logic level, architecture level and software level. Techniques like clock gating, operand isolation, write buffers, extensive power gating and voltage scaling coordinate to reduce power. The ARM architecture is tuned to minimize switching power.
SIMD and VFP
ARM includes single instruction multiple data (SIMD) instructions and a floating point unit (VFP) to improve performance for media and math functions. This allows fewer instructions to handle complex workloads which saves power compared to solutions without SIMD or FPU.
Thumb Instruction Set
The Thumb instruction set used in ARM processors condenses down ARM instructions into 16-bit formats. This increases code density and reduces memory accesses. The narrower instructions improve efficiency and reduce power consumption.
TrustZone Security
ARM TrustZone provides hardware-level security features while maintaining power efficiency. This allows secure transactions, DRM and authentication without a large power burden. Security features are implemented in hardware rather than software.
Core Configurations
ARM offers processors with different numbers of cores including single, dual, quad and octa-core configurations. Multi-core chips allow workload to be distributed across cores for performance and power savings. Individual cores can be power gated.
Integrated Memory Controller
Having an integrated memory controller on the SoC reduces memory access latency and power. External DRAM chips are low power themselves but require significant power for driving signals off-chip. An integrated controller avoids this.
Integrated Peripherals
ARM processors integrate common peripherals like interrupt controllers, timers, watchdog, and IO interfaces. Having these on-chip avoids external components and keeps peripheral access local reducing power. No external glue logic is required.
Small Die Size
The compact, efficient design of ARM processor cores results in a small silicon die size. For example, a quad-core Cortex-A53 cluster takes up less than 2% of a 28nm TSMC process. Small size directly results in lower leakage current and reduced power.
Tuning for Embedded Domain
ARM focuses its designs on the embedded computing market including mobile and IoT devices. Performance tuning for the embedded domain results in greater power efficiency than general purpose processors designed for high performance.
Synchronous Design
ARM processors use synchronous design methodology which makes extensive use of clock gating to prevent switching in idle circuitry. Clock gating can reduce processor power by 20-40% compared to asynchronous designs with global clocks.
System-on-Chip Design
By integrating an application processor, graphics, memory, and peripherals onto a single SoC, ARM enables low-power mobile devices. Keeping components on-die eliminates external interfaces. The SoC is optimized for the target device.
Software and Toolchain Optimization
ARM and its partners optimize the compiler, libraries, SDKs, and development tools to generate code that maximizes performance while minimizing power on ARM chips. Software optimization avoids inefficient routines.
Low Leakage Transistors
For leading edge process nodes like 14nm, 10nm, 7nm, transistor-level innovations reduce leakage current even when devices are active. Process optimizations boost energy efficiency of ARM’s CPU cores.
Summary
In summary, ARM processors are designed to provide high performance with low power across a variety of techniques. These include the RISC architecture, advanced pipelines, comprehensive power management, multi-core designs, efficient instruction sets, integrated components, small die sizes and process improvements. ARM’s focus on efficiency makes it ideal for mobile devices.
