Context switching refers to the process of storing and restoring the state or context of a processor when switching between executing multiple tasks or processes. In Arm Cortex processors, context switching enables multitasking by allowing the processor to pause execution of one task, save its context, and resume another task from where it left off.
Background on Arm Cortex Processors
Arm Cortex processors are central processing units (CPUs) designed by Arm for use in embedded systems and mobile devices. They are based on the Arm architecture and instruction set. Some key features of Arm Cortex processors relevant to context switching include:
- Reduced Instruction Set Computer (RISC) design – Simple and consistent instruction set optimized for lower power consumption.
- Load/store architecture – All operations are performed between CPU registers, not directly on memory locations.
- Banked registers – Multiple register banks for fast context switching.
- Exception handling – Support for interrupt handling to enable multitasking.
What Needs to be Saved During Context Switching?
When context switching between tasks, the processor needs to save essential details about the state of the current task being paused so it can resume from the same point later. The key components saved in Arm Cortex processors are:
- General purpose registers (R0-R12) – Store task-specific data like variables.
- Stack pointer (SP) – Points to the last stacked register on the stack.
- Link register (LR) – Stores return address after function calls.
- Program counter (PC) – Stores current instruction address.
- Processor status registers – Flags like interrupt enable, execution state, etc.
The context data is stored in a structure called the Process Control Block (PCB) for each task. This allows the task to be resumed from its last state by reloading the PCB.
Role of Banked Registers
Arm Cortex-M processors have up to 16 register banks to enable low latency context switching. While general purpose registers R0-R12 store task context, the current register bank is identified by the CONTROL register. This allows multiple tasks to have their contexts preloaded in different banks.
During a context switch, the processor simply changes the CONTROL register to switch banks, which automatically restores the new task’s context. This eliminates the need to save and restore individual registers to memory, speeding up context switching.
Context Switching Process
Here are the steps involved when context switching between two tasks A and B on an Arm Cortex processor:
- Task A is currently running. The processor receives an interrupt or exception indicating a switch to Task B.
- The processor saves its current state for Task A by pushing registers R0-R3, R12, LR, PC onto the current stack.
- The stack pointer (SP) is also saved, switching to Task B’s stack.
- The processor loads the CONTROL register for Task B’s register bank, restoring its saved context.
- Task B’s Program Counter (PC) and Link Register (LR) are loaded, resuming execution from where it left off.
- When another context switch occurs, the steps are reversed to save Task B and restore Task A’s context.
Context Switching Speed Optimization
The steps outlined above take time, during which the processor cannot execute instructions. Several techniques are used to optimize context switching speed in Arm Cortex processors:
- Banked registers – Avoid saving registers to memory by switching banked register sets.
- Tail-chaining – Link register supports chaining interrupt handlers without overhead.
- Fast interrupts – Set up interrupt handlers in Cortex-M to minimize latency.
- Configurable priority levels – Ensure right priority for low latency interrupts.
- Stack limit checking – Catch stack overflows across context switches.
Context Switching in a Real-Time Operating System
In a real-time operating system (RTOS) running on Arm Cortex, context switching occurs in the kernel or scheduling routine. It allows deterministic multithreading by coordinating context switches:
- A scheduler maintains a queue of runnable threads based on priority.
- Timer interrupts trigger the scheduler routine periodically.
- The scheduler suspends current thread and saves its context.
- The scheduler restores the context of the next thread to run.
- This allows real-time threads to share the processor at defined intervals.
RTOSes like FreeRTOS optimize context switching by minimizing the amount of data stored for each thread. Pre-emption also allows high priority threads to interrupt lower priority ones.
Benefits of Efficient Context Switching
Efficient context switching provides several benefits on Arm Cortex processors and RTOSes:
- Enables multitasking and parallel execution of multiple tasks/processes.
- Allows processor time sharing for real-time responsiveness.
- Fast and deterministic context switch time for RTOS threads.
- Higher overall throughput by executing tasks concurrently.
- Better power efficiency when tasks are idle and swapped out.
In summary, context switching leverages Arm Cortex’s architecture to save and restore task states efficiently. Optimized techniques enable low-latency switching critical for real-time systems. The result is responsive multitasking and execution concurrency within the constraints of a single processor core.