Cortex-M processors from Arm use the Thumb instruction set, which is a compact variant of the 32-bit Arm instruction set architecture (ISA). The Thumb ISA allows for higher code density compared to the 32-bit Arm ISA, while retaining most of the performance. This makes it well-suited for embedded applications where code size is a critical factor.
Overview of Arm Instruction Sets
Arm processors support multiple instruction sets:
- 32-bit Arm ISA – Original 32-bit instruction set used in early Arm processors. Instructions are 32 bits wide.
- Thumb ISA – Compact 16-bit instruction set introduced in Armv4T architecture. Provides higher code density while retaining most of Arm’s performance.
- Thumb-2 ISA – Extension of Thumb ISA in Armv6T2 architecture. Adds several 32-bit instructions to enhance performance.
- A32 – Refers to the original 32-bit Arm instruction set.
- T32 – Refers to the Thumb and Thumb-2 instruction sets.
The Thumb ISA was designed as a space-efficient alternative to the 32-bit Arm ISA. Thumb instructions are 16 bits wide instead of 32 bits, allowing for 2x the code density. Thumb-2 extended the Thumb ISA with selected 32-bit instructions for performance critical needs while retaining the space efficiency of 16-bit Thumb instructions.
Cortex-M Processors Use Thumb Instruction Set
All Cortex-M processor cores from Arm, including Cortex-M0, M0+, M1, M3, M4, M7, and M23/M33, implement the Thumb-2 instruction set. The Thumb-2 ISA builds on the original Thumb ISA and includes a mix of both 16-bit and 32-bit instructions. Here are some key points about the Thumb-2 ISA used in Cortex-M processors:
- Supports both 16-bit and 32-bit instructions.
- 16-bit Thumb instructions provide high code density.
- 32-bit instructions included for performance critical needs.
- Leverages ARMv6T2 architecture features like registers r8-r15.
- Includes Thumb-2 specific instructions like IT, CBZ/CBNZ.
- Cortex-M0/M0+ implement a limited Thumb-2 instruction set.
- Cortex-M1 and above implement the complete Thumb-2 ISA.
The mix of 16-bit and 32-bit instructions allows Cortex-M cores to achieve good performance without compromising code size. This is particularly important for memory constrained embedded applications. The compact 16-bit Thumb instructions maximize code density, while the 32-bit instructions provide access to more advanced operations and addressing modes.
Benefits of Using Thumb-2 ISA
Here are some of the key benefits provided by the Thumb-2 ISA used in Cortex-M processors:
- Higher code density – Up to 65% better code density than 32-bit Arm instructions.
- Small code size – More compact code lowers storage requirements and cost.
- Low power – Reduced memory accesses and better cache performance.
- High performance – 32-bit instructions deliver Arm performance when needed.
- Simplified migration – Gradual transition from legacy Arm code via interworking.
- Position independence – Uniform 16-bit size allows position independent code.
- Efficient execution – Streamlined execution using 16-bit instruction fetching.
In particular, the improved code density and reduced code size make the Thumb-2 ISA highly suitable for embedded Cortex-M devices. The small memory footprint allows developers to fit more functionality into limited flash and RAM budgets. Interworking support also simplifies migrating legacy Arm code over to Thumb-2 instruction set.
Interworking Between Arm and Thumb State
Cortex-M processors support interworking between Arm and Thumb instruction states. This allows branches between Arm and Thumb code within the same program. The program counter indicates the current instruction state:
- Lower bit = 0: Arm instruction state
- Lower bit = 1: Thumb instruction state
The BX and BLX instructions perform interworking branches by changing the lower bit of the program counter. Some key points on Arm/Thumb interworking:
- Low overhead branching using BX, BLX instructions.
- Gradual migration from Arm code to Thumb code.
- Ability to leverage legacy Arm libraries.
- Interworking not supported on Cortex-M0/M0+.
- Cortex-M3 and above fully support interworking.
This interworking ability is useful to leverage existing Arm code investments. Thumb-2 code can call Arm functions using BLX instructions. Or Arm code can gradually be ported over to Thumb-2 instruction set in incremental phases while retaining Arm libraries.
In summary, Cortex-M processor cores from Arm utilize the Thumb-2 instruction set based on the ARMv6-M/ARMv8-M architectures. Thumb-2 provides an optimal combination of high code density from 16-bit Thumb instructions and high performance from 32-bit instructions. The compact nature of the Thumb-2 ISA makes it ideally suited for embedded devices with tight memory constraints. Interworking support also simplifies integration with legacy Arm codebases. These characteristics have resulted in the dominance of Thumb-2 instruction set among modern Arm Cortex-M embedded processors.