Using SLEEPDEEP Bit to Select Sleep Mode on Cortex-M3

The Cortex-M3 CPU provides a SLEEPDEEP bit to allow flexible selection of sleep modes. Setting this bit allows the Cortex-M3 CPU to enter deep sleep mode, which offers the lowest power consumption. Clearing this bit causes the CPU to enter sleep mode instead, which has higher power consumption but faster wake-up time. This article provides a detailed guide on how to use the SLEEPDEEP bit to select between deep sleep and sleep modes during low power operation of a Cortex-M3 system.

Cortex-M3 Sleep Modes

The Cortex-M3 processor supports multiple low power modes to reduce power consumption during periods of inactivity. The two main sleep modes are:

• Sleep – The CPU, most peripherals and on-chip memories are powered off. The core can wake-up quickly but power consumption is higher than deep sleep.
• Deep Sleep – The CPU, all peripherals and memories are powered off. This provides the lowest power but wake-up time is longer than sleep mode.

The Cortex-M3 uses the SLEEPDEEP bit in the System Control Register (SCR) to select between sleep and deep sleep modes. When SLEEPDEEP=0, the CPU enters sleep mode. When SLEEPDEEP=1, the CPU enters deep sleep mode instead.

Entering Sleep vs Deep Sleep Mode

To enter sleep mode, the SLEEPDEEP bit must be cleared before the CPU goes to sleep. This sequence is used:

1. Clear SLEEPDEEP bit: SCR[SLEEPDEEP] = 0
2. Set SLEEPONEXIT bit if wake-up is needed on interrupt: SCR[SLEEPONEXIT] = 1
3. Execute WFI or WFE instruction to sleep the CPU

To enter deep sleep mode, the SLEEPDEEP bit must be set instead:

1. Set SLEEPDEEP bit: SCR[SLEEPDEEP] = 1
2. Set SLEEPONEXIT bit if wake-up is needed on interrupt: SCR[SLEEPONEXIT] = 1
3. Execute WFI or WFE instruction to put the CPU into deep sleep

Wake Up from Sleep vs Deep Sleep

The wake-up process from both sleep modes is similar. If the SLEEPONEXIT bit was set before sleeping, any interrupt will cause the CPU to wake-up. The interrupt return sequence restores the CPU registers and stack, allowing code execution to resume after the WFI/WFE instruction.

The main difference in wake-up between sleep and deep sleep modes is the time required. Sleep mode has faster wake-up latency as the CPU and core peripherals remain powered on. Deep sleep mode requires powering up the CPU, memories and peripherals which takes longer.

Therefore, deep sleep would be used when the lowest power consumption is critical, and the wake-up time is not as important. Sleep mode has higher power but can be useful for periodic wake-ups when fast response is needed.

Configuring Power Mode in ARM CMSIS Library

The ARM CMSIS libraries provide functions to easily configure sleep and deep sleep modes without directly modifying the SCR register. This allows for CPU-agnostic and portable sleep mode selection in firmware.

To enter sleep mode using CMSIS functions: //Clear POWER_DEEP_SLEEP bit to select sleep mode SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk //Sleep CPU __WFI();

For deep sleep mode: //Set POWER_DEEP_SLEEP bit to enable deep sleep SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk //Deep sleep the CPU __WFI();

The CMSIS libraries handle setting the SLEEPONEXIT bit based on interrupt priority levels. This allows for portable sleep mode selection across Cortex-M3 projects using ARM CMSIS functions.

Sleep Mode Power Consumption

Selecting between sleep and deep sleep modes involves a power vs performance trade-off. The current draw of the Cortex-M3 CPU in each mode is:

• Active – 26mA (MHz)
• Sleep – 330uA
• Deep Sleep – 4.2uA

Deep sleep has around 100x lower current than sleep mode. However, the wake-up latency is longer:

• Sleep wake-up – 2us
• Deep Sleep wake-up – 3us

For low frequency periodic wake-ups, sleep mode can provide fast enough response with lower impact on power consumption. Deep sleep would be optimal for always-on systems where CPU activity is very sporadic.

Factors that Impact Power Consumption

Besides the CPU sleep mode, other factors impact overall power consumption of a Cortex-M3 system:

• Clock Frequency – Higher CPU and peripheral clock rates increase active power proportionally.
• Peripheral Activity – Each active peripheral contributes to total current draw.
• Memory Access – External memory reads/writes consume more than internal memory accesses.
• Interrupt Activity – Frequent interrupts prevent the CPU from staying in sleep mode.

To optimize power consumption:

• Run the CPU at the lowest frequency needed for performance.
• Minimize external memory accesses.
• Disable unused peripherals or place them in low power mode.
• Consolidate interrupt service routines to limit wake-ups.

Real-Time Clock for Periodic Wake-Ups

A Real-Time Clock (RTC) peripheral is essential for systems that need periodic wake-ups from sleep or deep sleep modes. For example, a wireless sensor that transmits data every minute would use an RTC to wake the system at each transmission interval. The RTC continues running during sleep and generates interrupts to wake the CPU based on a programmed schedule. This allows the Cortex-M3 to sleep for a majority of the time and maximize power savings.

Optimizing Sleep Current for Battery Powered Devices

For battery-operated devices, the Cortex-M3 idle/sleep current directly impacts battery life. Some techniques to optimize the sleep current are:

• Minimize external components that draw power in sleep mode.
• Use low-power regulators and power supervisors.
• Use the lowest voltage for external memories and peripherals.
• Select packages and silicon with lower sleep/deep sleep current.
• Disable the PLL and high-speed clocks in sleep mode.
• Wake-up parts of the system sequentially to minimize inrush current.

With careful design, the Cortex-M3 idle/sleep current can be reduced to around 2uA. Combined with deep sleep mode, this can extend battery life on energy-constrained devices.

Software Flow for Low Power Operation

Here is an example software flow to utilize sleep and deep sleep modes on a Cortex-M3:

1. The application completes a task and has no immediate work pending.
2. The CPU prepares peripherals for sleep/deep sleep mode.
3. SCR SLEEPDEEP bit is configured for sleep or deep sleep.
4. WFI or WFE instruction issued to enter sleep/deep sleep mode.
5. A periodic RTC interrupt or external interrupt wakes the CPU after some time.
6. Interrupt service routine executed when CPU wakes up.
7. Scrubbing sequence to prepare peripherals for operation.
8. Application continues next task.

This allows the CPU to maximize time spent in low power modes between tasks and minimize active current.

Wake-Up Sources from Sleep/Deep Sleep

The Cortex-M3 can wake-up from sleep or deep sleep mode via:

• External interrupt from GPIO pin.
• Internal peripheral interrupts – RTC, ADC, Watchdog Timer etc.
• System reset signal.
• Direct Memory Access (DMA) requests on enabled channels.
• Debug system requests via SWD or JTAG port.

Using multiple wake-up sources allows the MCU to respond to a variety of system events while sleeping. Priority levels determine which interrupt causes immediate wake-up vs pending for next wake-up.

Debugging Sleep Related Issues

Some common issues when using sleep/deep sleep modes and how to debug them:

• CPU not waking up – Use oscilloscope to check the wake-up interrupt signal.
• High power consumption – Profile currents in active vs sleep modes to isolate issues.
• Peripheral malfunction after wake-up – Scrubbing sequence may need tuning for that peripheral.
• Spurious wake-ups – Multiple wake-up sources can cause conflicts.

A step-by-step debug approach can narrow down root causes of sleep related problems:

1. Confirm wake-up interrupt is actually asserted when expected.
2. Check sleep vs active power profile with multimeter/oscilloscope.
3. Inspect peripheral state before and after sleep.
4. Analyze sequence of events before and after wake-up.
5. Consult device errata for chip-specific anomalies.

Solving difficult low power bugs may require detailed analysis of firmware, peripherals, interrupts, and board layout to find the issue.

Sleep Mode Use Cases

Some examples where the Cortex-M3 sleep and deep sleep modes are commonly used:

• IoT Edge Nodes – Sleep allows duty cycling radio/network activity while minimizing power between transmissions.
• Wearables – Deep sleep extends battery life when user activity is sporadic.
• Wireless Sensors – Sleep/deep sleep maximizes life powered by batteries or energy harvesting.
• Remote Controls – Deep sleep minimizes current draw in always-listening remote/keyfob.
• Medical Devices – Sleep allows low power operation of intermittently used devices.

Overall, intelligent use of sleep and deep sleep modes allows the Cortex-M3 MCU to deliver advanced features and performance while optimizing power consumption for a target application.

Conclusion

The Cortex-M3 SLEEPDEEP bit provides flexible control over sleep vs deep sleep modes. Sleep allows fast wake-up while deep sleep offers the lowest power consumption. Combining these modes with intermittent peripheral operation, clock gating and power management allows the Cortex-M3 system to balance performance and power draw. This enables the M3 for use in a wide variety of power sensitive Internet of Things, wearable, medical, industrial and consumer applications.