Jamie Kellett

30 Articles

Cortex-M3 Instruction Prefetching and Branch Prediction (Explained)

The Cortex-M3 CPU implements an instruction prefetch unit and branch prediction unit to improve performance by reducing stalls due to

Jamie Kellett 14 Min Read

Qualcomm customizations of Cortex-A76 in Snapdragon SOCs

Qualcomm has made several customizations to the ARM Cortex-A76 CPU core in their Snapdragon system-on-chips (SOCs) to optimize performance and

Jamie Kellett 8 Min Read

Using SLEEPDEEP Bit to Select Sleep Mode on Cortex-M3

The Cortex-M3 CPU provides a SLEEPDEEP bit to allow flexible selection of sleep modes. Setting this bit allows the Cortex-M3

Jamie Kellett 11 Min Read

What is the Application Program Status Register (APSR) in Arm Cortex-M?

The Application Program Status Register (APSR) in Arm Cortex-M is a 32-bit register that contains application level status and control

Jamie Kellett 9 Min Read

Deciphering the (Cortex-M3) STM32F1 Vector Table when Booting from RAM

When booting a Cortex-M3 based STM32F1 microcontroller from RAM instead of flash memory, understanding how to properly configure the vector

Jamie Kellett 7 Min Read

Branch Instructions in ARM Cortex-M

ARM Cortex-M processors utilize branch instructions to alter the flow of a program by jumping to a new location in

Jamie Kellett 6 Min Read

Updating Board Files for Cortex-M0 DesignStart Eval r2p0 on MPS2+

The Cortex-M0 processor from ARM is an extremely popular 32-bit CPU optimized for low-power embedded applications. DesignStart Eval is a

Jamie Kellett 5 Min Read

Integrating AMBA Bus with Cortex-M1 in FPGA Designs

Integrating the AMBA (Advanced Microcontroller Bus Architecture) bus with a Cortex-M1 processor core in an FPGA (Field Programmable Gate Array)

Jamie Kellett 10 Min Read

Is Arm Better Than X64?

The debate between Arm and x64 architectures has been going on for years in the tech industry. Both have their

Jamie Kellett 7 Min Read

What are Co-processor instructions in Arm Cortex-M series?

Co-processor instructions in Arm Cortex-M series microcontrollers provide an interface to optional co-processors that can be added to the core

Jamie Kellett 8 Min Read

What are TrustZone security instructions in Arm Cortex-M series?

TrustZone security instructions in Arm Cortex-M series processors provide hardware-based security features to enable trusted execution environments and partition sensitive

Jamie Kellett 6 Min Read

What are Single-cycle I/O port in Arm Cortex-M series?

Single-cycle I/O ports in Arm Cortex-M series microcontrollers allow data to be written to or read from the port in

Jamie Kellett 7 Min Read
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