The Application Program Status Register (APSR) in Arm Cortex-M is a 32-bit register that contains application level status and control information. It provides details on the condition flags from previous instruction executions as well as information on the current processor state. The APSR allows monitoring and control of application programs in Arm Cortex-M processors.
Overview of the APSR
The APSR is generally used to check the status of the conditional flags and the current processor mode. It contains several fields that provide this information:
- N – Negative flag
- Z – Zero flag
- C – Carry flag
- V – Overflow flag
- Q – Saturation flag
- GE – Greater than or Equal flags
- Mode – Indicates current processor mode
The condition flags (N, Z, C, V) are set by instruction executions and indicate the result of operations. For example, an ADD instruction that results in a negative result will set the N flag. These flags can be tested by conditional instructions to alter program flow.
The Q and GE flags are related to DSP operations and indicate saturation or pass/fail results on those type of instructions.
The Mode field indicates the current processor mode – Thread, Handler, etc. This informs debuggers and monitors of the current program state.
By reading the APSR, a program can check the status flags, saturation conditions, or processor mode very efficiently with a single register access. The flags in the APSR are useful for optimizing branches, loops, and conditionally executed code.
APSR Register Format
The APSR register format is as follows: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | N | Z | C | V | Q | | Mode |
- Bits 31-28 – Condition flags (N, Z, C, V)
- Bit 27 – Saturation flag (Q)
- Bits 26-24 – Reserved
- Bits 23-16 – Greater than or Equal flags (GE)
- Bits 15-0 – Processor mode field
The condition flags in bits 31-28 provide the negative (N), zero (Z), carry (C), and overflow (V) status flags. These flags are updated after most data processing instructions like ADD, SUB, etc. They can be tested using conditional execution instructions like BEQ, BGT, etc.
Bit 27 contains the Q flag which indicates saturated results. It is set if a DSP saturating instruction saturates the result.
Greater Than or Equal Flags
Bits 23-16 contain the GE flags which are used for DSP threshold compare instructions. A bit in this field is set if the comparison passes for that number.
Processor Mode Field
The lower 16 bits contain the current processor mode encoding. This indicates if the processor is in Thread mode, Handler mode, or another supported mode.
Reading the APSR
To read the APSR, the MRS (Move to Register from Special Register) instruction is used like: MRS R0, APSR
This will copy the value in the APSR to general purpose register R0 where it can be examined. The condition flags, mode, and other fields will be present in the R0 register value.
For example: ; Execute instruction that sets condition flags ADD R1, R2, R3 ; Read APSR into R0 MRS R0, APSR ; R0 now contains flags/mode from APSR
Writing the APSR
To write to the APSR, the MSR (Move to Special Register from Register) instruction is used like: MSR APSR, R0
This will copy R0 into the APSR to set the condition flags and other fields. Note that some bits like the Q flag cannot be set directly by software.
For example: ; Create value to write to APSR in R0 MOV R0, #0xF00000 ; Copy R0 to APSR MSR APSR, R0 ; APSR now has flags/mode from R0
Using the APSR Flags
The condition flags in the APSR are used to conditionally control program flow and execution. Some examples include:
- Branching on zero (BEQ)
- Branching on positive/negative (BPL, BMI)
- Compare and branch on equal (CBNE)
- Conditional selection (IT/SEL)
Based on the flags from a previous instruction, a conditional instruction can execute or be skipped. This avoids having to explicitly compare a value in a register.
For example: ; Perform subtractions SUBS R1, R2, R3 ; Branch on negative (N flag set) BMI failure ; Branch on zero (Z flag set) BEQ done ; Continue if positive number
The SUBS instruction sets the N and Z flags which are automatically tested by the conditional branching. No explicit compare is needed against R1.
APSR in Exception Handling
The APSR plays an important role in exception handling on Cortex-M processors. When an exception occurs:
- The current value of the APSR is automatically saved to the stacked PSR
- The exception handler runs
- The APSR is restored on exception return
This ensures the flags and status are preserved across the exception. The handler code can also view the stacked PSR to inspect the APSR at the time of the exception.
Interaction with xPSR
The xPSR (extended PSR) is a special register that contains the APSR along with the IPSR and EPSR registers. When code reads/writes the xPSR, it is accessing the APSR component specifically.
For example: MRS R0, xPSR ; Read xPSR into R0 ; R0 bits 31-28 contain APSR condition flags ; R0 bits 24-16 contain APSR GE flags ; R0 bits 15-0 contain APSR mode field
The xPSR can be thought of as a larger register that encompasses the APSR (along with IPSR and EPSR).
Tips and Tricks
Here are some useful tips for working with the APSR register:
- Use MRS and MSR to read and write the APSR efficiently.
- Test condition flags to optimize conditional code and minimize explicit compares.
- Inspect stacked xPSR values in exception handlers to view APSR contents.
- Set PUSH and POP instructions to automatically save/restore APSR for function calls.
- Utilize LDM and STM to save and restore multiple registers including APSR.
- Combine conditional execution with APSR flag tests for very efficient if/then code.
The Application Program Status Register (APSR) contains important condition flags, status bits, and mode settings for monitoring and controlling application programs. By leveraging the APSR, developers can optimize code flow, handle exceptions, and simplify conditional execution. The APSR is a powerful tool available in all Cortex-M processors that should be utilized to its full potential.
Understanding the format fields of the APSR provides the foundation for effectively applying it within application code. The ability to quickly read and write the APSR using MRS and MSR allows setting up and testing the flags. Exception handling relies on the automatic stacking of the APSR on interrupts to preserve the state. And the APSR integrated within xPSR gives a full view of the current processor status.
Overall, mastering usage of the Application Program Status Register helps unlock the performance and efficiency benefits of conditional execution, optimized branching, streamlined interrupt handling, and more on Arm Cortex-M processors.