RTL (Register Transfer Level) simulation allows designers to verify the functionality of their ARM Cortex-M0, M3 and M4 designs before manufacturing the IC. It provides a software model that mimics the behavior of the hardware so developers can test it thoroughly in a virtual environment. RTL simulation is a critical part of the IC development workflow.
Introduction to RTL Simulation
RTL simulation refers to simulating the register transfer level description of a digital circuit. It models the flow of digital signals between hardware registers and the logical operations performed on them. RTL abstraction provides a good tradeoff between simulation speed and accuracy compared to gate-level or transistor-level simulations.
The ARM DesignStart chips like Cortex-M0, M3 and M4 are provided as RTL models for simulation and synthesis. The RTL code is written in Verilog or VHDL languages. It describes the functional behavior of the processor without detailing the exact gates or transistors.
Some key benefits of RTL simulation are:
- Faster simulation compared to lower level models
- Earlier software development as hardware need not be ready
- Finds functional bugs before manufacturing the IC
- Allows testing corner cases thoroughly
- Facilitates hardware/software co-development
Simulation Flow for ARM Cortex-M DesignStart
The typical simulation flow for DesignStart Cortex-M involves:
- Obtaining the RTL code from ARM
- Adding custom logic and memory blocks
- Writing testbenches to stimulate the interfaces
- Running functional verification against specifications
- Developing drivers for peripherals, interrupts, etc.
- Integrating processor with system level DUT model
- Co-simulating RTOS, application software
- Assessing code performance, utilization
The RTL code is simulated by adding testbenches to drive stimulus and monitor results. A testbench instantiates the DesignStart RTL, interfaces it to models of external logic and memories using transactor modules. Bus functional models (BFMs) are used to initiate and respond to transactions.
The test cases generate stimulus vectors that are applied to the inputs of the DUT. Output signals are captured and compared against expected results to verify correct functionality. Any mismatches are flagged as errors.
Challenges in RTL Simulation
Some key challenges faced in simulating ARM Cortex-M RTL are:
- Long simulation time due to detailed processor models
- Complex test scenarios like interrupt handling, power modes
- Corner case testing to find obscure bugs
- Synchronization between RTL, testbench and software
- Limited hardware debug capability compared to emulation
- Difficulty in identifying root cause of errors
The RTL simulation must factor in real world use cases along with boundary and corner cases to fully verify the design. Memory models can account for a large portion of simulation time. Techniques like using fast models, simulation acceleration, emulation, formal verification etc. help overcome the challenges.
Simulation Tools for ARM DesignStart
Some commonly used EDA tools for simulating ARM Cortex-M DesignStart RTL are:
- Mentor Graphics ModelSim
- Synopsys VCS
- Cadence Incisive Enterprise Simulator
- Aldec Active-HDL
- Silicon Labs Simplicity Studio
These tools compile the RTL code and run the testbench stimulus to execute the simulation. Some benefits offered are:
- Supports Verilog, VHDL, SystemVerilog standards
- Has ARM bus model libraries for AHB, APB, AXI, etc.
- Good debugging visibility into signals and variables
- Integration with popular HDL editors and frameworks
- Assertion capabilities for formal verification
The tools also offer advanced capabilities like simulation acceleration, hardware-assisted verification, virtual prototyping interfaces, formal analysis integrations and more.
Developing Testbenches and Stimulus
A key step is developing robust testbenches to verify the DesignStart Cortex-M RTL functionality. The testbench instantiates the DUT, interfaces it to the test harness and generates stimulus to the inputs of the DUT. Some best practices are:
- Use bus functional models to initiate bus transactions
- Parametrize stimulus using random variables
- Generate corner cases using constraints
- Add delays on interface signals to model timing
- Monitor assertions continuously to catch bugs early
- Use coverage metrics to gauge completeness of verification
The stimulus patterns should cover typical real life scenarios as well as stress cases to robustly verify the design. Error injection can simulate faulty behavior. Formal analysis can complement simulation for specific requirements.
Software Development and Co-Simulation
A key benefit of RTL simulation is enabling early software development before the hardware is ready. The processor RTL model can be used to boot an RTOS, run device drivers, exercise peripherals and develop application firmware.
Transaction level models (TLMs) model the behavior of external interfaces. These are co-simulated along with the RTL to provide an executable environment for the software stack. This allows hardware/software integration issues to be caught early.
The simulated environment helps profile software execution, memory usage, interrupt latency and task scheduling. It facilitates debugging and performance optimization of the firmware. Co-simulation provides a complete virtual prototype of the SoC for early software development.
Integrating Cortex-M RTL with DUT
The DesignStart processor RTL will be integrated with the rest of the SoC logic and memories while developing the full IC. The ARM core acts as a master/bus initiator to interact with the custom slave peripherals and memory blocks in the system.
Transactor based testbenches are developed to model the behavior of the external slave interfaces. These are co-simulated along with the Cortex-M RTL to verify the complete SoC functionality. SoC integration may require adapting the ARM bus interfaces to proprietary internal protocol.
The RTL simulation verifies the integrated system behavior in terms of overall functionality, performance, bandwidth, throughput, utilization and other parameters. This robust architecture validation is crucial before manufacturing the SoC.
RTL simulation enables thorough verification of the design functionality and early software development, which are critical to ensure first-time success for ARM Cortex-M tapeouts. A robust methodology leveraging advanced verification techniques and tools is key to enable comprehensive pre-silicon validation and hardware/software co-development.
The virtual prototype created by RTL simulation provides valuable insights and confidence in the design before manufacturing the IC. This results in faster time-to-market, lower development cost and higher quality for ARM Cortex-M based SoCs.