The Cortex-M1 is an ARM processor core that is commonly used in embedded systems. It has a simple memory map with distinct regions for code, data, peripherals, and external memory interfaces. The Cortex-M1 supports mapping an external DDR (double data rate) memory region into its physical address space to extend available memory beyond internal SRAM and integrated flash memory.
Overview of Cortex-M1 Memory Map
The Cortex-M1 processor contains an embedded memory management unit (MMU) that controls the mapping of addresses to physical memory regions. The standard Cortex-M1 memory map consists of the following regions:
- 0x00000000 – 0x1FFFFFFF: Code region for flash memory and ROM
- 0x20000000 – 0x3FFFFFFF: SRAM region for data and stack
- 0x40000000 – 0x5FFFFFFF: Peripheral region for registers
- 0x60000000 – 0xDFFFFFFF: External device region
- 0xE0000000 – 0xFFFFFFFF: System region and vendor specific
The external device region from 0x60000000 – 0xDFFFFFFF is used to map external memories like external flash, RAM, and peripherals. This is the region where an external DDR memory would be mapped.
DDR Memory Interface
To connect external DDR memory to the Cortex-M1 processor, a DDR memory controller is used. This controller handles the DDR protocol and provides a simple external bus interface to the processor. The controller connects to the processor’s system bus matrix, allowing transactions to be routed to the DDR memory.
The DDR memory controller will expose a contiguous address space that corresponds to the DDR memory chip capacity. For example, for a 128MB DDR chip, the controller may provide a 128MB address space from 0x60000000 – 0x67FFFFFF.
Mapping External Memory in MMU
To map the external DDR memory region into the processor’s address space, the Cortex-M1’s memory management unit (MMU) is configured. This is done by configuring the MMU’s memory region attributes and address mapping registers.
There are 16 definable regions in the Cortex-M1 MMU. Each region is defined by setting the start and end address, memory attributes (cacheable, bufferable, etc), and the map address. The map address specifies where the region appears in the processor’s physical address map.
For example, to map a 128MB DDR memory from 0x60000000 – 0x67FFFFFF, the following steps would be taken:
- Select an unused MMU region, such as region 10
- Set region 10 start address to 0x60000000 and end address to 0x67FFFFFF
- Set attributes to: cacheable, bufferable, no execute, external memory
- Set region 10 map address to 0x60000000
With this MMU configuration, the processor would see the external 128MB DDR memory mapped into its physical address range 0x60000000 – 0x67FFFFFF.
Enabling MMU and Regions
Once the MMU regions are configured properly, the MMU must be enabled to activate the address mappings. This is done by setting the MMU Control Register enable bit.
Individual MMU regions can also be enabled/disabled by setting the enable bit in each region’s attribute register. Regions are disabled by default at reset.
Accessing Mapped DDR Memory
With the DDR memory mapped into the processor’s address space, it can then access the external memory identically to internal SRAM or flash. Reads and writes to addresses 0x60000000 – 0x67FFFFFF will be routed to the external DDR memory controller.
The processor handles arbitration and sequencing to access the DDR memory controller. The controller then interfaces with the physical DDR chips, issuing the required commands to perform the requested read or write operation.
From the processor perspective, accessing a mapped address results in a transaction on the AHB system bus. The DDR controller responds to the transaction and takes over external memory access. This allows the memory to appear as part of the standard physical address space.
Optimizing DDR Memory Performance
Several steps can be taken to optimize DDR memory performance when mapped to a Cortex-M1 processor:
- Enable MMU caching for the DDR region – this avoids redundant external accesses
- Use DMA to perform large sequential transfers
- Align data structures to DDR burst size
- Group code and data in DDR appropriately
- Use prefetch buffering and caching if available
- Tune DDR controller parameters for optimal timing
Properly configuring the MMU attributes is also important. The bufferable, cacheable, shared attributes should be set based on the application’s memory access patterns.
Potential Issues to Be Aware Of
Some potential issues to keep in mind when mapping DDR memory to a Cortex-M1 processor:
- External memory transactions impact real-time performance
- Need to ensure no overlapping MMU regions
- DDR requires periodic refresh cycles to maintain data integrity
- Must initialize DDR controller properly for reliable operation
- Memory contention if multiple masters access DDR simultaneously
With careful configuration of both the processor MMU and DDR controller, along with optimized access patterns, many of these potential pitfalls can be avoided.
Cortex-M1 Address Space Summary
In summary, the Cortex-M1 MMU allows flexible mapping of external DDR memory into the processor’s physical address space. The external device region from 0x60000000 – 0xDFFFFFFF is well suited for mapping large external memories.
The MMU configuration process sets the region start/end address, attributes, and map address to define the location the external memory will appear in the address space. Once enabled, the processor can seamlessly access the mapped DDR.
Careful consideration should be given to optimization techniques and potential issues to ensure the external DDR memory performs as an efficient extension of the Cortex-M1’s memory map.
With the ability to map external DDR memory, the Cortex-M1 can support much larger and faster memory capacities than its internal SRAM and flash alone. This enables more complex and demanding embedded applications to leverage high performance memory.