How to change endianess settings in cortex m3?

The endianess setting in Cortex-M3 processors refers to the byte order used to store data in memory. Cortex-M3 supports both little endian and big endian byte ordering. To change the endianess setting, the SCTLR configuration register needs to be modified. This can be done through the CPU registers or configuration code.

Overview of Endianess

Endianess refers to the sequence in which bytes are arranged in memory for larger data types like shorts, ints, longs etc. There are two types of endianess:

• Little Endian – The least significant byte is stored at the smallest memory address. Used by Intel x86.
• Big Endian – The most significant byte is stored at the smallest memory address. Used by Motorola 68k.

For example, the hex number 0x12345678 would be stored in memory as: Little Endian: 0x78 0x56 0x34 0x12 Big Endian: 0x12 0x34 0x56 0x78

The Cortex-M3 processor supports both endian formats. The default is little endian but this can be changed to big endian if required.

Endianess Configuration Register

The endianess mode in Cortex-M3 is controlled by bit 9 of the System Control Register (SCTLR). This is located at address 0xE000ED04 in the System Control Space. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—|—| | RES0| TE | AFE | TRE | NMFI | EE | VE | RES0 | U | FI | IT | V | RR | C | A | M | RES0|SW|B| RES0|EE|IE|

Bit 9 controls the EE bit:

• 0 – Little Endian mode
• 1 – Big Endian mode

All other bits should be left at their reset values when changing the endianess configuration.

Changing Endianess via CPU Registers

To change the endianess mode at runtime, the SCTLR register needs to be modified directly. This requires the following steps:

1. Read the current value of the SCTLR into a CPU register using MRC instruction:
2. Modify bit 9 of the value in r0 to change endianess mode. 1 for big endian, 0 for little endian.
3. Write back the new value to the SCTLR using MCR instruction:

This will immediately change the endianess mode for the Cortex-M3 processor. All subsequent load and store instructions will use the new byte order.

Changing Endianess at Startup

The endianess mode can also be configured at startup before the main application runs. This ensures the correct mode is set prior to any data processing by the application.

To set the mode at startup:

1. Enable access to coprocessor 10 and 11 in your startup code before enabling interrupts:
2. Set the EE bit in the SCTLR to the desired endian mode:
3. Proceed with remaining system startup code

This configures the Cortex-M3 to use big endian byte order right from bootup. The endianess cannot be changed afterwards unless the SCTLR is modified at runtime.

Checking Current Endianess

To check the currently configured endianess mode, the SCTLR value can be read and bit 9 examined: MRC p15, 0, r0, c1, c0, 0 ; Read SCTLR into r0 // r0[9] = 0 means little endian // r0[9] = 1 means big endian

The endianess mode directly affects load/store instructions, so a simple read of a known value can also be used: LDR r0, =0x12345678 // r0 = 0x12345678 little endian // r0 = 0x78563412 big endian

Endianess Considerations

There are some important considerations when changing the endianess in Cortex-M3:

• All exceptions and interrupt handlers will run in the configured endian state
• Changing the state at runtime can cause issues if data was previously loaded with the opposite endianess
• Endianess applies to all bus accesses – so peripherals, memory, etc will all be affected
• Multiprocessor endianess synchronization requirements if Cortex-M3 interacts with other processors
• May break interactions with debugger if debugger is not configured for same endian state

Therefore, endianess configuration is best set during system initialization and not dynamically changed during runtime for most applications. The default little endian mode is appropriate for most needs.

Example Code for Endianess Change

Here is example C code to demonstrate changing the endianess mode in Cortex-M3 at startup: // Enable CP10 and CP11 for MCR access __asm volatile(“mrc p15, 0, r0, c1, c0, 2”); __asm volatile(“orr r0, r0, #(1 << 10)”); __asm volatile(“orr r0, r0, #(1 << 11)”); __asm volatile(“mcr p15, 0, r0, c1, c0, 2”); // Set SCTLR.EE bit to 1 for big endian mode __asm volatile(“mov r0, #0x00000100”); __asm volatile(“mcr p15, 0, r0, c1, c0, 0”); // Remainder of startup code // …. // Application code runs in big endian mode // Can check with: __asm volatile(“mrc p15, 0, r0, c1, c0, 0”); if(r0 & (1<<9)) { // Big endian mode } else { // Little endian mode }

Summary

Changing the endianess mode in Cortex-M3 requires modifying the EE bit in the SCTLR configuration register. This can be done directly via the CPU or during startup initialization code. The mode affects all subsequent load/store instructions. Little endian is most commonly used, but big endian is available if required. Endianess should not be dynamically changed once the application has started due to data and peripheral interface concerns.