Bit banding is a useful feature in ARM Cortex M3 and M4 processors that allows individual bits within the memory map to be aliased to a single physical word in bit band region. While this provides atomic read-modify-write access to peripheral registers, overusing bit banding can lead to performance problems and timing issues.
What is Bit Banding?
The Cortex M3 and M4 processors include a 1MB section of physical SRAM called the bit band region. This region maps each bit within the lower 32MB of the memory map to its own physical word in the bit band SRAM. For example, bit 0 of address 0x2000 4000 is aliased to word address 0x2200 0000 in the bit band region. This allows that particular bit to be accessed atomically using a single 32-bit read-modify-write instruction.
Bit banding is useful for setting or clearing individual bits in peripheral registers or memory-mapped I/O without risk of intermediate states. For example, to set bit 5 of the GPIO port A data register, you could write to the bit band alias address 0x2220 0014 instead of the actual peripheral register address 0x4000 4010. This performs an atomic read-modify-write operation.
Dangers of Overusing Bit Banding
While bit banding seems like an easy way to manipulate peripheral registers, overusing it can cause problems:
Every bit band access requires multiple memory transactions on the peripheral bus. This includes a read from the bit band region, a modify, and a write-back. Even if the peripheral register is cached, it still requires bus transactions to maintain coherency.
Frequently accessing peripheral registers via bit band aliases can therefore limit the maximum bus frequency. The Cortex M3/M4 only supports up to 3 bit band accesses per clock cycle. Excessive bit band usage can starve other bus masters and lower overall performance.
Bit band accesses take multiple cycles to complete. This can cause problems with peripherals that require strictly timed sequences. For example, writing to a timer load register via a bit band alias may take too many cycles, causing erratic behavior.
Some peripheral registers like FIFOs or DMA controllers require atomic back-to-back writes. Bit banding does not guarantee atomicity between separate accesses. This can corrupt state machines or data streams.
Increased Memory Usage
Frequent bit band access reserves space in thevaluable 1MB bit band region. This reduces memory available for other usages like RAM stacks, buffers, etc. Bit band space is wasted if the aliased peripheral registers are rarely accessed.
Accessing peripheral registers through complex bit band address calculations bloats code size. This is especially true if bit banding is used inside interrupt handlers or other performance-critical routines.
The compiler may also have trouble optimizing bit band address calculations. A simple peripheral register write can turn into many instructions.
Bit banding can still be useful if applied correctly. Keep these best practices in mind:
Use Bit Banding Judiciously
Reserve bit banding for critical bits that require atomic RMW, like interrupt enables/disables. Avoid arbitarily bit banding all peripheral registers.
Group Bit Band Accesses
If multiple bit band accesses are required, group them together to maximize bus utilization. Separate groups of bit band accesses with non-aliased instructions.
Avoid Excessive Bit Band Usage
Measure performance with profiler tools to quantify bit band overhead. Tune software architecture if bit bands exceed 3 accesses per clock cycle.
Use Bit Banding for Infrequent Events
Bit band writes to static configuration registers or status registers that are not bandwidth-critical.
Do Not Use Bit Banding for Time-Critical Access
Avoid bit banding for registers that require precise timing like timers, PWMs, DMA, etc. Use non-aliased peripheral register writes.
Consider Performance Requirements
In performance-critical software like audio algorithms, bit band sparingly to avoid starving other bus masters. Prefer non-aliased accesses.
Allocate Bit Band Space Wisely
Only allocate bit band space for frequently accessed peripheral registers. Balance with other SRAM usage.
Bit banding can provide atomic access to peripheral registers, but overuse can cause performance issues and timing problems in Cortex M3/M4 designs. Use bit band aliases judiciously, measure bus utilization, and prefer non-aliased accesses when possible. With careful application of bit banding, developers can build high-performance and robust Cortex M3/M4 systems.