The Cortex-M0+ processor implements two stack pointers, known as the Main Stack Pointer (MSP) and Process Stack Pointer (PSP). These stack pointers enable low-latency context switching between different execution threads or tasks running on the Cortex-M0+ core.
MSP and PSP Overview
The MSP is used to store the context of exception handlers and privileges software executing in Thread Mode. This includes the exception stack frame, register contents, and stack for the OS privileged code. The PSP stack pointer is used by user threads executing in Handler Mode using the PSP. When a context switch occurs between threads, the PSP of the previous thread is saved and the PSP of the new thread is restored. This enables each thread to maintain its own stack.
Benefits of MSP and PSP
- Faster context switching by restoring PSP instead of reconfiguring MSP.
- Thread stack overflow does not corrupt other thread stacks.
- Simplifies stack management for multithreaded programs.
- MSP use in Thread Mode improves real-time performance.
Context Switching Procedure
The steps to perform a context switch between two threads using MSP and PSP on Cortex-M0+ are:
- The context switch is triggered by an OS timer interrupt or other RTOS event.
- The interrupt handler executes in Thread Mode using MSP.
- The handler saves context of current thread’s registers to stack or memory.
- The stack pointer PSP value is saved to the thread control block.
- PSP is restored from new thread’s control block.
- Registers for new thread are restored from stack or memory.
- EXEC_RETURN instruction returns to new thread using updated PSP.
- The new thread executes in Handler Mode until next context switch.
The critical steps during context switch are saving and restoring the PSP value. This switches the stack pointer from current thread to new thread. The register context is also stored and reloaded, enabling continuation of each thread.
Context Switch Time
The Cortex-M0+ processor can perform extremely fast context switches due to its simplified architecture. Typical context switch times are:
- 12 cycles from interrupt to first instruction in handler.
- 4 cycles to save a general purpose register to stack.
- 2 cycles to load a general purpose register from stack.
- 2 cycles to save and restore PSP.
This enables Cortex-M0+ context switches in less than 30 cycles or 1 microsecond at common operating frequencies. This low overhead allows implementing real-time OS kernels and multi-threaded applications on Cortex-M0+ MCUs.
RTOS Context Switch Implementation
Real-time operating systems will utilize the MSP and PSP to enable optimal context switching on Cortex-M0+. Some key implementation points:
- OS runs privileged code on MSP in Thread Mode.
- User threads run on PSP in Handler Mode.
- PSP is changed to new thread stack during context switch.
- OS kernel saves PSP to thread control block or TCB.
- TCB holds PSP, stack pointer, registers.
- OS enter and exit to switch modes and stack pointers.
This keeps real-time kernel code isolated on MSP and user threads separated on PSP. MSP use optimizes real-time performance in Thread Mode. The RTOS handles saving and restoring PSP and register context during scheduling.
RTOS kernels will be specifically optimized for Cortex-M0+ context switching. This includes:
- Streamlined save/restore of minimal context.
- Use of EXEC_RETURN handler entry/exit.
- Tuning interrupt handling for low latency.
- Dedicated OS Tick timer and handler.
- Kernel code optimized for Cortex-M0+ execution.
With proper RTOS implementation, Cortex-M0+ enables extremely responsive real-time multithreaded applications.
Bare Metal Context Switching
The MSP and PSP stack pointers can also be leveraged for context switching without an RTOS:
- All shared system code runs on MSP in Thread Mode.
- Each thread has independent PSP stack area.
- Main loop triggers context switches on timer.
- Save context and PSP to/from global struct.
- Set PSP to new thread stack pointer value.
- Reload context and return to thread code.
This bare metal technique provides basic context switching. However, it lacks RTOS features like scheduling, resource management and synchronization.
The Cortex-M0+ dual stack pointers enable fast context switching critical for real-time applications. MSP optimizes privileged code execution. PSP allows multiple threads to have independent stack areas. By saving and restoring PSP and register context, low-overhead context switches under 30 cycles are possible. RTOSes can leverage the architecture for responsive multithreaded performance.