Configuring and optimizing threads and stacks for the Keil RTX real-time operating system (RTOS) when using the ARM Cortex-M0+ microcontroller can improve performance and resource utilization. The key considerations are configuring the number of threads, stack size for each thread, kernel tick frequency, thread priorities, and utilizing stack watermarking.
Overview of Keil RTX and Cortex-M0+
The Keil RTX RTOS is designed for ARM Cortex-M microcontrollers. It provides preemptive multi-threading with configurable scheduling policies. The Cortex-M0+ is one of the smaller and more resource constrained Cortex-M variants, so optimizing RTX configuration is especially important.
Key features of RTX on Cortex-M0+:
- Supports up to 31 threads
- Fixed priority preemptive scheduling
- optionally utilizes CMSIS-RTOS API
- Small memory footprint starting around 1.5KB
Configuring Number of Threads
The maximum number of threads supported is 31. However, utilizing fewer threads can reduce memory usage and context switching overhead. The optimal number depends on the application requirements.
Considerations for number of threads:
- Memory usage – each thread requires a stack and kernel control block
- Context switching overhead – more threads means more frequent switching
- Logical separation – separate threads for logically distinct tasks
- Priority levels needed – fixed priority scheduling limits priority levels to number of threads
- Performance goals – more threads can allow greater parallelism
For many applications, 4-8 threads provide a good balance. Critical tasks can be separated while minimizing overhead.
Configuring Stack Size for Threads
The stack size for each thread must be configured based on the thread’s requirements. The factors to consider are:
- Local variables used by the thread
- Nested function calls within the thread
- Interrupt handler requirements if thread utilizes interrupt
- OS overhead for context switching and kernel calls
In general, starting with a 512-1024 byte stack and increasing based on testing is recommended. The Cortex-M0+ has limited RAM so using larger stacks than required wastes memory.
RTX provides stack watermarking which can track the maximum stack usage for tuning. The watermark stack size in RTX config should be set to the initial stack size guesses.
Kernel Tick Frequency
The RTX kernel tick interval controls context switching between threads. It is triggered by a periodic timer or hardware interrupt. The tick frequency should be high enough to meet application responsiveness needs.
Guidelines for kernel tick frequency:
- 10-100Hz typical range
- Higher for faster thread switching
- Must be higher than longest task duration
- Higher frequency increases CPU load
Starting at 100Hz tick and reducing based on application performance is recommended. The tick frequency sets the minimum thread time slice.
RTX uses fixed priority preemptive scheduling. Higher priority threads always run before lower priority threads. Matching thread priorities to meet application requirements is important.
Guidelines for assigning thread priorities:
- Most critical tasks get highest priority
- Prioritize real-time tasks over non-real-time
- Assign similar priorities to threads with similar criticality
- Spread priorities over range for flexibility
- Consider priority inversion avoidance
Starting with priority levels matched to logical importance and then tuning based on performance is recommended.
Optimizing with Stack Watermarking
The RTX stack watermarking feature tracks the maximum stack usage for each thread. It can be enabled in the RTX configuration.
Use stack watermarking to:
- Identify initial stack size guesses
- Tune stack sizes to minimize waste
- Detect stack overflows during testing
Monitoring stack usage over typical program execution and then setting stack sizes slightly above watermarks will optimize memory usage.
Optimizing RTX configuration and threads is key to maximizing performance on resource constrained Cortex-M0+ MCUs. Adjusting the number of threads, stack sizes, kernel tick rate, thread priorities and utilizing stack watermarking based on profiling and testing can enable efficient utilization of the Cortex-M0+ capabilities.
With careful configuration, the RTX RTOS can provide robust multi-threading on the Cortex-M0+ to meet requirements for responsiveness, real-time performance, and logical task separation. The flexibility of RTX makes it suitable for a wide range of Cortex-M0+ applications.