Neil Salmon
SWD-Port of the Cortex-M0: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval
The "SWD-Port of the Cortex-M0: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval" error indicates an issue with connecting to…
Cortex M0 Returning from Interrupt
When an interrupt occurs on a Cortex M0 processor, the processor must handle the interrupt properly by saving its current…
How to Activate the Debug Viewer for Cortex-M0?
The Cortex-M0 is an ultra low power 32-bit ARM processor core designed for microcontroller applications. It is optimized for low…
Cortex M0+, AHB state during Exception
The Cortex-M0+ processor from Arm is an ultra low power 32-bit RISC CPU core designed for microcontroller applications. It builds…
How generic are Cortex-M0+ MCUs?
Cortex-M0+ microcontrollers (MCUs) from ARM offer a good balance of performance, power efficiency, and cost for a wide range of…
How to Create a Hard Fault Handler that Prints Out Call Stack on Cortex-M0+?
When a hard fault occurs on Cortex-M0+, it is critical to be able to print out the call stack to…
Hard Fault Handler Problem – Cortex-M0+
The Cortex-M0+ processor from ARM is an extremely popular 32-bit microcontroller that is used in a wide range of embedded…
ARM Cortex M0(PGA970) set Primask/disable interrupts
The ARM Cortex-M0 is an ultra low power 32-bit ARM processor core designed for microcontrollers and deeply embedded applications. It…
Faster way of multiplying 2 32-bit numbers giving a 64-bit result in Cortex M0/M0+
Multiplying two 32-bit numbers to get a 64-bit result is a common operation in many embedded and IoT applications running…
Does setting a section’s attributes using MPU affect the CPU’s ordering of the specific section?
Setting a section's attributes using the Memory Protection Unit (MPU) can affect the CPU's ordering of that specific section. The…
Does Normal memory, and Device memory really affect the system behavior? Cortex M0/M0+
The simple answer is yes, the type of memory used - normal or device - can affect system behavior on…
Steps Required to do Synthesis and FE Sign-off of ARM Cortex M0
The synthesis and front-end (FE) sign-off process for an ARM Cortex-M0 design involves several key steps. At a high level,…
