The Arm Cortex-M4 processor is a popular 32-bit microcontroller core used in a wide range of embedded systems. As with any complex processor design, the Cortex-M4 has had some issues discovered after release, documented in official errata notices from Arm. While most of these are minor bugs, some can cause problems in certain applications, so Cortex-M4 users need to be aware of relevant errata items. This article provides an overview of key Cortex-M4 errata and how to work around them.
Arm publicly documents all functional problems with its cores. Errata notices list issues that affect correct functional operation and may require workarounds in hardware, firmware, or both. Most errata only occur in specific corner-case conditions. Each erratum has an ID number and description. They are grouped into categories:
- Processor errata affect core execution
- Debug errata affect debug/trace logic
- Memory system errata affect caches or TCMs
- System errata affect interfaces between core and system
For Cortex-M4, the most important errata are in the processor category. These can cause instruction faults, incorrect execution results, or change structures like the stack. Debug, memory, and system errata are less likely to directly cause problems in applications. But they can still break debugging or introduce subtle memory corruption issues.
The Cortex-M4 has over 50 documented errata. Below are some of the most significant issues to be aware of:
- Erratum 709718: Stack pointer corruption during exception entry/return
- Erratum 752770: Incorrect bit-field insert instruction encoding
- Erratum 776924: Vector fetch can overtake vector return
- Erratum 838869: Possible fault on WL/SSAT instruction at maximum saturation value
- Erratum 843419: Saturation faults not detected following multiply accumulate
- Erratum 717302: Debug halt after CoreDebug_DHCSR_C_DEBUGEN cleared
- Erratum 725631: Limitations of flash patch and breakpoint support
Memory System Errata
- Erratum 798870: Data corruption possible with store-exclusive to full cache line
- Erratum 801120: Speculative instruction fetches with MPU can read out-of-range
For full details on these and other errata, refer to the official Arm documentation. The highest severity errata should be reviewed in detail.
Where possible, Arm defines software workarounds for errata. Cortex-M4 code may need to implement workarounds for specific errata impacting an application. Some techniques include:
- Avoiding the specific instruction sequences that trigger an erratum
- Inserting extra instructions to avoid the internal processor state that hits an erratum
- Changing linker scripts or stack/heap allocation to avoid buggy memory regions
- Modifying compiler code generation flags to avoid generating problematic code sequences
- Updating CPU operation mode to alter memory access size or instruction timing
Silicon vendors implementing the Cortex-M4 in custom chips may also make hardware changes to fix errata, so check vendor documentation. Errata are tracked across processor revisions. More recent cores fix some older errata, but may also introduce new ones.
Example Workaround – Erratum 843419
As an example, Erratum 843419 can cause a fault exception when the Cortex-M4 executes a multiply-accumulate instruction where the accumulation would saturate the result. Saturation faults may not occur when expected. The workaround is to insert an extra “CLRPS” instruction after any multiply-accumulate that could saturate: SMULL R1,R2,R3,R4 // R1 = R3 * R4 ADC R5,R5,R2 // Accumulate product Low halfword ADDS R5,R5,R1, LSL #1 // Accumulate product High halfword CLRPS // Clear saturation flag (workaround for erratum 843419)
This resets the saturation flag to avoid unexpected faults later in code. All Arm errata have similar code sequence recommendations to avoid the bug triggering.
To identify errata relevant to your specific Cortex-M4 implementation:
- Check the core revision – newer revisions fix more errata
- Review the silicon vendor’s chip errata documentation
- Read the Arm processor errata for that core revision
- Focus on errata with high severity ratings
- Assess whether your code uses sequences that could trigger bugs
- Implement workarounds in code, compiler, or linker settings as needed
Staying up-to-date on new processor errata notices is also important. Arm may release new errata against existing architectures as bugs are discovered. Monitoring and quickly adopting errata workarounds helps build robust Cortex-M4 designs.
Arm Cortex-M4 errata can cause subtle and hard-to-diagnose software issues. Errata documentation provides crucial details for working around processor bugs. While most errata require specific conditions to trigger, care should be taken to avoid those conditions in production code when possible. Implementing recommended software workarounds and monitoring for new errata helps mitigate the chance of problems. Overall, the Cortex-M4 has relatively few errata that impact typical applications, but engineers should still be aware of potential exceptions in complex use cases.