The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. The Cortex-M instruction set architecture provides a simple, easy-to-use instruction set optimized for low-cost embedded applications. It focuses on simplicity, low power consumption, and reduced code size while maintaining good performance.
Overview of Cortex-M Instruction Set
The Cortex-M instruction set is based on the Thumb-2 instruction set first introduced in ARMv6 architecture. It uses a variable length encoding with 16-bit and 32-bit instructions. The instruction set consists of:
- Data processing instructions like add, subtract, compare, move, etc.
- Load/store instructions for accessing data in memory
- Branch instructions like branch, branch with link, etc.
- Supervisor call and exception generating instructions
- Coprocessor instructions for accessing specialized functional units
- SIMD instructions for improved parallelism and signal processing
The Cortex-M ISA utilizes a load/store architecture where data processing operations only work on processor registers. All instructions are conditional, meaning execution can be skipped based on status flags. The instruction set provides a limited but useful set of registers including 13 general purpose registers and a program counter among others.
Data Processing Instructions
Data processing instructions are used to perform basic arithmetic, logical, and move operations on registers and immediate constants. These include:
- Addition and subtraction (ADD, SUB)
- Logical operations (AND, ORR, EOR)
- Comparison (CMP, CMN, TST)
- Shifts and rotates (LSL, LSR, ASR, ROR)
- Move register (MOV)
- Bit field manipulation (BFC, BFI)
The data processing instructions can utilize register or immediate operands. They operate on the general purpose registers R0-R12. Conditional execution based on status flags is supported. These instructions provide the essential data manipulation capabilities for most embedded applications.
As a load/store architecture, the Cortex-M ISA contains various instructions for transferring data between memory and registers. Load operations copy memory contents into a register, while store operations copy a register to memory. The load/store instructions include:
- Byte loads/stores (LDRB, STRB)
- Halfword loads/stores (LDRH, STRH)
- Word loads/stores (LDR, STR)
- Load/store multiples (LDM, STM)
Loads and stores utilize a variety of addressing modes like immediate offsets, register offsets, pre/post-indexing, and PC-relative addressing. This allows flexible access to variables located at different memory offsets. The load/store architecture reduces code size compared to traditional CISC ISAs.
Branch instructions alter the sequential instruction flow by changing the program counter to a target address. The Cortex-M branch instructions include:
- Branch (B)
- Branch with Link (BL, BLX)
- Compare and Branch (CBZ, CBNZ)
Branches can utilize PC-relative offsets or register indirect addressing. BL and BLX instructions store the return address in the link register for function calls. Compare and branch instructions perform an implicit comparison against zero before branching. Overall, the branching capabilities enable non-sequential control flow in programs.
Exception and System Instructions
The Cortex-M ISA contains instructions to handle exceptions/interrupts and perform system related operations. These include:
- Supervisor Call (SVC)
- Breakpoint (BKPT)
- Wait For Event/Interrupt (WFE, WFI)
- No Operation (NOP)
SVC and BKPT allow software to trigger exceptions and breakpoints for OS context switches or debuggers. WFE and WFI instructions can be used to enter low power states until an event or interrupt occurs. NOP can be used for instruction padding and timing delays. These system instructions enable critical OS and power management capabilities.
Coprocessor and SIMD Instructions
The Cortex-M architecture allows implementation defined coprocessors with their own specialized instruction sets. Common coprocessors include the Floating Point Unit (FPU) and Memory Protection Unit (MPU). SIMD instructions can also be optionally implemented for improved parallel processing of multimedia data.
Typical SIMD instructions include:
- Integer addition/subtraction (SADD, SSUB)
- Multiply with accumulate (SMLA)
- Saturating arithmetic (SSAT, USAT)
- Pack and unpack data (SADDLP, UZP1)
By performing the same operation on multiple data elements concurrently, SIMD instructions greatly boost math-intensive code like multimedia processing and computer vision algorithms.
The Cortex-M instruction set provides a versatile foundation for embedded microcontrollers requiring low cost and power consumption. Its variable length Thumb-2 encoding offers a good code density vs performance tradeoff. From basic data processing and memory access to branches, exceptions and SIMD, the ISA enables high efficiency implementations tailored for embedded systems.