The Cortex-M0+ and Cortex-M0 are both low-power 32-bit microcontroller cores from ARM aimed at embedded and IoT applications. The main difference between the two is that the Cortex-M0+ has additional features and enhancements that make it more capable and efficient than the older Cortex-M0.
Overview of Cortex-M0 and Cortex-M0+
The Cortex-M0 and Cortex-M0+ are both ARMv6-M architecture compatible cores belonging to ARM’s Cortex-M series of processors. They are designed for microcontroller and deeply embedded applications requiring low cost and power consumption.
The Cortex-M0 was introduced by ARM in 2009 as their first low-power microcontroller core. It was designed to enable ARM’s partners to develop low-cost 32-bit MCUs to compete with 8-bit and 16-bit microcontrollers in cost-sensitive applications.
The Cortex-M0+ was launched in 2012 as an enhanced replacement to the Cortex-M0. It retains code compatibility with the Cortex-M0 but adds several new features aimed at better performance and power efficiency.
Key Differences Between Cortex-M0 and Cortex-M0+
Here are some of the major differences between the two cores:
- The Cortex-M0+ has a two-stage pipeline while the Cortex-M0 has a single-stage pipeline. This enables faster instruction execution in the M0+.
- The M0+ incorporates microarchitectural changes to reduce dynamic power consumption by up to 25% compared to the M0.
- The M0+ includes new single-cycle I/O interfaces like bit-banding and interrupt clear registers to reduce latency and code size.
- The M0+ supports up to 16 interrupt priority levels compared to only 2 levels in the M0.
- The M0+ includes optional memory protection unit (MPU) and micro trace buffer (MTB) blocks to enhance application robustness and debug.
- The M0+ core can be implemented in lower gate counts and reduced die sizes compared to the M0.
Architectural Improvements in Cortex-M0+
Let’s look at some of the microarchitectural improvements in the Cortex-M0+ over the Cortex-M0:
The Cortex-M0 used a single-stage pipeline which meant that every instruction had to go through the same execution stage. The Cortex-M0+ incorporates a two-stage pipeline which allows for better pipelining and enables faster instruction execution.
In the M0+, one instruction can be fetched while another is being decoded and executed. This improves performance especially for repetitive loops allowing for higher clock frequencies.
Operand Forwarding Path
An operand forwarding path is added in the Cortex-M0+ between the decode and execute pipeline stages. This path forwards the results of instructions directly to the execution stage without having to writeback and then read from the register file.
This improves performance by eliminating stalls and bubble cycles when dependent instructions are issued back-to-back.
Low Gate Count Design
The Cortex-M0+ implements logic and datapath optimizations to reduce overall gate count and die area. For example, the register file in M0+ requires fewer gates and less power compared to the M0.
The optimized design enables the Cortex-M0+ core to be implemented in smaller silicon chips, resulting in lower costs for silicon partners.
Dynamic Power Saving
Multiple techniques are used in the Cortex-M0+ to reduce dynamic power consumption compared to Cortex-M0:
- Operand isolation detects unused operands in instructions and prevents switching of associated datapath bits.
- Input register isolation disables inputs to functional units when they are not required.
- Early decode termination avoids unnecessary decode operations for specific instructions.
- Sticky prediction improves branch prediction accuracy to avoid mispredictions.
Together these optimizations significantly reduce the core’s dynamic power consumption making it ideal for power-sensitive embedded applications.
Feature Set Comparison
|Max clock frequency||50 MHz||50 MHz|
|Memory protection unit||No||Optional|
|Data watchpoint unit||No||Optional|
|Trace support||No||Optional (MTB)|
|Interrupt levels||2||Up to 16|
|Wakeup interrupt controller||No||Optional|
As seen above, the Cortex-M0+ retains code compatibility with Cortex-M0 but incorporates a number of microarchitectural enhancements as well as additional optional features.
Performance and Efficiency Comparison
Let’s compare the performance and efficiency of the two cores:
- Higher DMIPS/MHz: Cortex-M0+ provides up to 15% higher DMIPS/MHz than Cortex-M0 owing to the faster two-stage pipeline.
- Faster interrupt handling: M0+ has lower interrupt latency and faster exception entry/exit compared to M0.
- Lower dynamic power: M0+ consumes up to 25% lesser active power than M0 due to microarchitectural optimizations.
- Lower silicon area: M0+ can be implemented in up to 30% smaller silicon area and lower gate counts than M0.
- Higher energy efficiency: The combination of higher performance and lower power makes the M0+ significantly more energy efficient.
Overall, the Cortex-M0+ delivers better performance and improved power efficiency compared to the older Cortex-M0 core.
Use Cases and Applications
Here are some typical use cases where Cortex-M0+ and Cortex-M0 cores are commonly used:
- Cost-sensitive microcontroller units (MCUs) for home appliances, toys, etc.
- Sensors, actuators, and other simple embedded devices in industrial automation.
- Motor control applications like brushless DC motors, stepper motors, etc.
- Low-bandwidth IoT edge nodes for automation, asset tracking, environment monitoring etc.
- Simple wearable devices like fitness bands, smart watches, etc.
The Cortex-M0+ is generally preferred over M0 for new cost-sensitive designs owing to its better performance and efficiency. However, the Cortex-M0 remains popular for very low-cost applications as well as for legacy designs.
In summary, the Cortex-M0+ builds upon the success of the Cortex-M0 with a two-stage pipeline, lower dynamic power, and additional features for enhanced real-time performance. It retains full code compatibility for easy migration from M0 designs.
For new embedded microcontroller designs, the Cortex-M0+ should generally be preferred over the older Cortex-M0 except for some very cost-sensitive applications where the smaller silicon area of the M0 may still be beneficial.