The ARM Cortex-M Exception Program Status Register (EPSR) is a key register that controls exception and interrupt handling in Cortex-M processors. It indicates the current processor state and tracks exception-related information to assist with exception entry and exit. Understanding the EPSR is crucial for developers working with Cortex-M devices.
Overview of the EPSR
The EPSR is a 32-bit read/write register present in all Cortex-M processors. It contains several bit fields that serve the following key functions:
- Indicating the current processor operating mode
- Tracking the active exception number
- Storing interrupt masking state
- Providing software interrupt bits for triggering interrupts
- IndicatingStack Alignment status on exception entry
The EPSR works closely with the Interrupt Program Status Register (IPSR) to manage exception processing. On exception entry, the EPSR receives a copy of the previous IPSR value, which becomes the exception number field. The EPSR mode bits are also updated to reflect the handler mode. On exception return, the EPSR’s exception number is copied back to the IPSR to restore the pre-exception state.
EPSR Register Format
The EPSR register contains the following bit fields: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N Z C V Q ICI/IT T Exception Number Software Interrupt Requests Stack Alignment Fault
- Bits [31:27] – Reserved. Reads as zero, writes are ignored.
- Bits [26:25] – Execution state bits. N, Z, C, V flags.
- Bit 24 – Overflow or sticky overflow bit.
- Bit 23 – Execution state bit for CSPR.Q.
- Bits [22:20] – Exception number field. Contains IPSR value on exception entry.
- Bits [19:16] – Software interrupt request bits.
- Bit 15 – ICI/IT bit. Controls exception behavior.
- Bits [14:10] – Reserved.
- Bit 9 – Stack alignment status bit.
- Bits [8:0] – Processor mode field. Indicates handler mode.
Key EPSR Bit Fields and Functions
Processor Mode Bits
The processor mode field, bits [8:0], indicates the current privilege level and processor mode. On exception entry, these bits are updated to match the handler mode. The possible mode values are:
- 0x0 – Thread mode
- 0x1 – Reserved
- 0x2 – Reserved
- 0x3 – Privileged Thread mode
- 0x7 – Reserved
- 0xB – Reserved
- 0xF – Handler mode
Bits [22:20] contain the exception number corresponding to the current exception. This field receives a copy of the IPSR value on exception entry. Possible exception numbers are:
- 0x0 – Thread mode
- 0x1 – Reserved
- 0x2 – Non-maskable Interrupt (NMI)
- 0x3 – HardFault
- 0x4-0xF – Reserved
- 0x10-0x1F – External interrupts IRQ(0) to IRQ(15)
Software Interrupt Bits
The software interrupt bits [19:16] can be used to trigger exceptions and interrupts in software. Setting these bits to 1 causes the corresponding exception to enter pending state:
- Bit 16 – Request NMI exception
- Bit 17 – Request HardFault exception
- Bit 18 – Request MemManage exception
- Bit 19 – Request BusFault exception
Stack Alignment Bit
Bit 9 indicates stack alignment status on exception entry. It is set to 1 if the SP is not 8-byte aligned on exception entry.
How the EPSR Manages Exceptions
Here is how the EPSR assists with exception handling:
- Exception occurs and is pending.
- EPSR receives a copy of the IPSR value in its exception number field [22:20].
- EPSR mode bits [8:0] are updated to the handler mode.
- Stack alignment bit 9 set if needed.
- Processor switches to handler mode and execution.
- On exception return, EPSR exception number copied back to IPSR.
- EPSR mode bits restored to pre-exception value.
- Execution resumes in original mode.
This coordinated saving and restoring of the EPSR and IPSR is fundamental to nested exception support in Cortex-M. The EPSR tracks just enough state to assist handlers, without duplicating the full register context like a stack frame.
Software Usage of the EPSR
Although the EPSR is managed by hardware during exceptions, software can utilize the register in several ways:
- Check EPSR mode bits to identify handler mode.
- Examine stack alignment bit to check for 8-byte stack alignment.
- Trigger software interrupts by setting interrupt request bits.
- Read exception number to identify active exception.
- Modify EPSR execution state bits for conditional execution.
For example, a HardFault handler may check the stack alignment bit and exception number to help determine the cause of the fault. The execution state bits can also be changed to affect conditional branching.
Typical Operations on the EPSR
Here are some common operations on the EPSR register in Cortex-M firmware:
- MRS – Move EPSR contents to a general purpose register
- MSR – Move general purpose register contents to EPSR
- ORR – Set software interrupt bits
- MOVS – Modify flags based on EPSR.N,Z,C,V
- BEQ – Branch based on EPSR.Z flag state
// Read EPSR MRS R0, EPSR // Trigger NMI interrupt MOV R1, #1 ORR R1, R1, #0x10000 MSR EPSR_nzcvq, R1 // Branch based on EPSR.Z BEQ error_handler
EPSR Access Privileges
The EPSR can be accessed at all privilege levels in Thread mode. However, in Handler mode, the EPSR can only be accessed at PL2 or higher privilege. This prevents thread code from erroneously modifying the EPSR state within interrupt handlers.
EPSR in ARMv6-M
For ARMv6-M Cortex-M0/M0+ processors, the EPSR register only implements a subset of the bit fields described above. The software interrupt bits, stack alignment bit, and Q bit are not implemented. The functionality is otherwise identical to ARMv7-M implementations.
In summary, the EPSR is a crucial component of the Cortex-M exception model. It maintains just enough state to assist exception entry and exit, while keeping the context switching overhead minimal. Understanding how to leverage the EPSR can help developers write optimized interrupt handlers and low-level software on Cortex-M devices.