The ARM Cortex-M3 is a 32-bit processor core licensed by ARM Holdings. It is part of the Cortex-M series of cores, and is designed for embedded applications requiring high performance and low power consumption. The Cortex-M3 core has a 3-stage pipeline and includes features like Thumb-2 instruction set, optional Memory Protection Unit (MPU), and nested vectored interrupt controller (NVIC).
The Cortex-M3 implements the ARMv7-M architecture and has a Von Neumann architecture with a unified address space for instructions and data. It has separate instruction and data buses to allow simultaneous access to both program and data memory. The memory organization of Cortex-M3 can be divided into following regions:
Code Memory (Flash)
This refers to the non-volatile memory region which stores the executable program code. It is typically implemented using flash memory and occupies the lower part of the address space starting from 0x00000000. The size of code memory can vary from 32KB to 1MB based on the IC vendor and target application requirements. Cortex-M3 supports both on-chip and external flash memory for code storage.
The Cortex-M3 integrates SRAM memory for data storage which is volatile in nature. The SRAM region occupies the upper part of processor’s address space. A minimum of 32KB SRAM is required by the core architecture. The size can scale upto several MB for external memories. SRAM memory is further divided into following regions:
This memory region holds the stack data used by a program for function calls, return addresses, local variables etc. Stack grows from higher address to lower address. The SRAM region just below the heap is used as stack memory.
This refers to the dynamic memory allocation region used for malloc and new type of functions. The heap grows from lower address to higher address within SRAM region. The heap size is configurable and application specific.
BSS and Data Sections
The uninitialized and initialized global & static variables are stored in BSS and Data sections respectively as per the executable file format. These sections are present at the lower part of SRAM region.
Peripheral Memory Region
This memory region is used to map the registers of on-chip peripherals like GPIO, timers, I2C, SPI etc. This region occupies some address space within SRAM region. The peripherals are memory mapped for easy access from software.
Memory Mapped Registers
In addition to peripheral registers, the Cortex-M3 memory map also contains various system control registers. These are used for core configuration, clocking, interrupts, debugging etc. Some of the important memory mapped registers include:
- System Control Space (SCS) Registers – Includes CPUID, Interrupt Controller Type, SysTick registers etc.
- Nested Vectored Interrupt Controller (NVIC) Registers – Used for enabling interrupts and reading status.
- System Control and ID (SCB) Registers – Includes important registers like Application Interrupt and Reset Control (AIRCR), Memory Protection Unit (MPU) etc.
- Debug Halting Control and Status Register (DHCSR) – Used for debugging via breakpoints.
Embedded SRAM vs External SRAM
As mentioned earlier, Cortex-M3 can have SRAM either integrated on-chip referred as embedded SRAM or external SRAM ICs can be interfaced for higher memory size. The on-chip SRAM has lower latency and consumes less power. But it is limited in size. The external SRAM offers higher capacity but has to be interfaced using a bus interface. The choice depends on application memory requirement.
Memory Access Bus
The Cortex-M3 core connects to memory via AHB-Lite bus which supports high-performance single-cycle data transfers. It has separate 32-bit data and address buses. For on-chip memories, this bus is directly connected. For external memories, the AHB-Lite bus needs to be converted to appropriate external memory bus protocol using a system bus matrix.
The memory interface of Cortex-M3 supports little endian byte ordering natively. Though big endian configuration is also possible using relevant control bits.
Memory Protection Unit
The optional Memory Protection Unit (MPU) in Cortex-M3 provides support for protecting memory regions from access violations. Up to 8 protected regions can be configured with individual permission control. This helps create a robust memory map for reliable application execution.
Caching and Tightly Coupled Memories
The Cortex-M3 does not contain internal caches. So memory reads & writes happen directly. However, Tightly Coupled Memories (TCM) interface is provided to integrate fast SRAM blocks with single cycle access latency. These TCMs can be used for time critical code or data storage.
The memory layout of Cortex-M3 application is defined using linker scripts. The script specifies the start address, length and access permission for each memory region. It places the code, data, stack, heap and other sections accordingly. The template linker script provided by the IC vendor needs to be modified as per the target memory map.
For debugging the program code, Cortex-M3 supports breakpoint and watchpoint exceptions. The breakpoints can be set at instruction addresses whereas watchpoints monitor data accesses within a memory range. This generates debug events which can be used by a debugger or ICE equipment.
Embedded Memory Interface
The on-chip memories like flash and SRAM are interfaced to the core using standard memory signals. These include address bus, data bus, chip select signals, read/write strobes and ready feedbacks. The exact signalling depends on memory technology used.
External Memory Interface
For connecting external memories, the AHB-Lite bus needs to be converted to external bus protocols like synchronous/asynchronous SRAM, NOR flash, NAND flash, parallel SDRAM etc. based on memory devices used. This is done using system bus matrix, external bus bridges and relevant I/O signalling.
Memory Map Configuration
The memory map is configured using a Memory Mapping Tool as part of system development process. This tool allows specifying memory regions, assigning sections/peripherals and generating requisite configuration files. These configuration files are used by the linker script to place application components correctly.
Typical Memory Map
A typical Cortex-M3 memory map looks as follows with flash and SRAM regions along with peripherals and registers mapped: 0x2000_0000——————————- On-chip Peripherals | . | . 0x1FFF_FFFF——————————- | 0x2002_4000——————————- External Peripherals . | . . | 0x2000_0000——————————- | 0x0000_0000——————————- Code (Flash) . | . . | 0x2000_0000——————————- SRAM | . | . 0x2001_C000——————————- Heap (grows upwards) | 0x2001_8000——————————- Stack (grows downwards) | 0x2001_4000——————————- BSS Section | 0x2001_0000——————————- Data Section | . | . 0x2000_2000——————————- Peripheral Registers
This covers the key aspects related to memory organization on the ARM Cortex-M3 processor. The flexible memory architecture along with memory protection enables robust and optimized implementation of embedded applications on this processor core.