ARM processors utilize interrupts extensively to handle events and peripherals. There are two main interrupt controller systems used in ARM processors – the Nested Vectored Interrupt Controller (NVIC) and the Generic Interrupt Controller (GIC). The key differences between NVIC and GIC are:
1. NVIC is used in Cortex-M processors, GIC is used in Cortex-A processors
NVIC is found in ARM’s Cortex-M series of processors which are designed for microcontrollers and embedded applications. These are lower power, lower performance processors meant for real-time control tasks.
GIC is found in ARM’s Cortex-A series which are higher performance application processors aimed at running operating systems like Linux or Android. The Cortex-A series is used in mobile devices and other battery-powered gadgets.
2. NVIC supports nesting while GIC does not
NVIC allows interrupt nesting, which means a higher priority interrupt can preempt a lower priority interrupt handler which was already running. This helps ensure real-time responses for the most critical events.
GIC does not support nesting. If an interrupt occurs while another handler is running, it will simply be ignored or latched for later processing. For Cortex-A application processing, interrupt nesting is generally not needed.
3. NVIC has fixed priority levels, GIC has configurable priorities
NVIC supports a fixed number of priority levels, usually 256. Interrupts are strictly prioritized based on their assigned priority level.
GIC has configurable priority bits, typically 8. This allows priorities to be tuned for a specific OS or application. GIC also groups interrupts into security domains, allowing secure and non-secure interrupts.
4. NVIC is tightly integrated with the processor, GIC is more independent
NVIC is designed to be very low latency and deterministic. It is integrated into the Cortex-M processor itself. This allows very fast interrupt handling, critical for real-time performance.
GIC is a more standalone design with its own interface. It provides flexibility but higher latency. Latency is less critical for application processor workloads focused on throughput.
5. NVIC only handles peripheral IRQs, GIC handles additional events
NVIC solely handles standard peripheral IRQ interrupts. It does not handle any other exception or event processing.
GIC handles peripheral IRQs but also provides support for other sources like software generated interrupts (SGIs), performance monitoring interrupts, virtual interrupts from a hypervisor, etc.
6. NVIC is simpler, GIC supports more features
NVIC has a streamlined design to support real-time low latency interrupt handling. It has limited flexibility or configurability.
GIC has many more features like prioritization, security, virtualization, multi-core support, message-based interrupts, doorbells, etc. This comes at the cost of higher latency.
7. NVIC provides fixed exception handling, GIC is flexible
NVIC has dedicated exception vectors for different types of exceptions like reset, faults, SVCall, etc. Handling is standardized for Cortex-M.
GIC allows flexibility configuring the targets of interrupts and events. For example virtual interrupts from a hypervisor can be injected as desired.
8. NVIC shares registers with the CPU core, GIC has separate registers
NVIC control registers are integrated with the ARM core’s register file. This improves determinism but means NVIC cannot be accessed independently.
GIC has its own set of memory mapped control registers allowing it to be accessed independently and even shared between multiple cores.
9. NVIC requires no external logic, GIC benefits from additional logic
NVIC requires no external glue logic, reducing board complexity and cost. The NVIC interfaces directly with peripherals.
GIC integrates with other system logic like the Interrupt Translation Service to handle more complex multi-core interrupt handling and prioritization needs.
10. NVIC suits simple embedded systems, GIC suits advanced OS use-cases
In summary, NVIC fits the requirements of embedded microcontrollers well. It emphasizes real-time determinism and low-latency handling of peripheral IRQs.
GIC is designed to support more advanced OS use cases where flexibility, features, and security are needed. The cost is higher latency interrupt handling.
The type of interrupt controller used depends on the ARM processor family and intended use case. NVIC for Cortex-M microcontrollers, GIC for Cortex-A application processors running complex OSes like Linux.
NVIC Technical Details
Here are some key technical details on ARM’s Nested Vectored Interrupt Controller used in Cortex-M processors:
- Integrated with the processor for low latency interrupt handling
- Priority based preemptive scheduling of interrupts
- Up to 256 priority levels with 0 being highest priority
- Nested interrupts allow real-time preemption
- Tail-chaining optimizes back-to-back interrupt handling
- Vector table maps interrupts to handler addresses
- Programmable priority grouping for efficient prioritization
- External interrupts routed through NVIC from peripherals
- Enables, disables and sets pending status of interrupts
- Written in ARM Thumb-2 instruction set for efficiency
- Cortex-M processor implementable as uncore for ASICs/SoC
- Used in ARM M0, M3, M4, M7, M23, M33 processor cores
GIC Technical Details
Here are some key technical details on ARM’s Generic Interrupt Controller used in Cortex-A processors:
- Flexible prioritization with 8-bit priority field per interrupt
- Split into Distributor and CPU interfaces
- Distributor handles multi-core synchronization
- Configurable priority grouping via Distributor
- Security domains provide register partitioning
- Doorbell interrupts for inter-processor messaging
- Message-based interrupts with additional data
- Legacy PPI (Private Peripheral Interrupt) support
- Virtualization features to support hypervisors
- Performance monitoring and profiling triggers
- Can target different CPU interfaces allowing flexibility
- Used in Cortex-A5, A7, A8, A9, A15, A17, A32, A35, A55, A57, A72, A73 cores
Typical NVIC Usage
Here is an example of how NVIC would typically be utilized in a Cortex-M microcontroller:
- NVIC is integrated on-chip with the Cortex-M processor
- Vector table maps interrupts to handler functions
- Software assigns priority levels to peripheral interrupts
- External peripherals assert IRQ lines connected to NVIC
- On interrupt, NVIC suspends main program flow
- NVIC jumps to corresponding handler based on vector table
- Handler runs to completion or is preempted by higher priority IRQ
- NVIC returns to main program flow after handler finishes
- Short predictable interrupt latency for real-time response
This fixed priority IRQ handling model allows real-time firmware to respond quickly and predictably to critical events triggered by on-chip or external peripherals.
Typical GIC Usage
Here is an example of how GIC would typically be used in a Cortex-A application processor:
- GIC integrated as a separate block on SoC
- Linux kernel driver programs priorities and configurations
- Peripherals route through bus to GIC Distributor
- Distributor handles multi-core synchronization
- Interrupt Translation Service can handle further system priority
- GIC CPU interface targets processing cores
- Linux handles interrupt servicing using configured schemes
- Higher latency but very flexible interrupt handling
- Supports complex OS and hypervisor environments
This programmable model is used to enable Linux, Android, RTOS and hypervisor support on multi-core SoC application processors with many peripherals.
In summary, NVIC and GIC take different approaches to interrupt handling on ARM chips due to the different requirements of Cortex-M and Cortex-A processors.
NVIC emphasizes real-time low latency handling for embedded microcontrollers. GIC offers advanced flexibility and features for complex operating systems.
Understanding the differences between these two interrupt controllers provides insights into ARM’s product portfolio spanning from tiny microcontrollers to multi-core application processors.