The ARM Cortex-R52 is the latest processor core in ARM’s real-time Cortex-R series. It is designed for high-performance real-time and safety-critical applications that require deterministic timing behavior and freedom from interference. The Cortex-R52 builds upon the previous Cortex-R generations, bringing significant improvements in performance, power efficiency, and architectural features.
Some key highlights of the ARM Cortex-R52 include:
- Dual-issue superscalar pipeline capable of issuing 2 instructions per cycle
- Out-of-order execution engine with a re-order buffer size of 72
- 8-stage integer pipeline and 11-stage floating point pipeline
- Clock speeds up to 3 GHz on a 5nm process node
- Scalable Vector Extension (SVE) for vector processing
- Enhanced Floating Point and NEON processing capabilities
- Hardware virtualization support
- Enhanced reliability, availability and serviceability (RAS) features
The Cortex-R52 is Arm’s first R-series core with out-of-order execution capabilities. This allows more efficient use of the processor’s execution resources and helps increase performance. The core can decode and dispatch up to 6 instructions per cycle to the various execution pipelines.
Compared to the previous generation Cortex-R82, ARM claims the Cortex-R52 achieves a 60% performance uplift on EEMBC CoreMark benchmarks. Power efficiency is also improved with a 35% increase on CoreMark/mW. On compute-heavy workloads, the performance improvements can be even higher thanks to the out-of-order engine and dual-issue capabilities.
The Cortex-R52’s floating point and DSP capabilities have also been enhanced with a redesigned NEON Processing Engine that can execute most instructions in a single cycle. Single and double precision floating point throughput is significantly boosted through the NEON unit.
For workloads that can take advantage of vector parallelism, the Cortex-R52 implements Arm’s new SVE technology. SVE allows variable length vectors from 128 to 2048 bits. This allows better tuning of vector lengths for optimal performance and power efficiency across different use cases.
While adding more advanced microarchitectural capabilities like out-of-order execution can potentially interfere with deterministic real-time behavior, Arm has focused on enhancing the Cortex-R52’s real-time capabilities compared to previous R-series generations:
- The core implements microarchitectural isolation to prevent timing variations from leaking across contexts. This includes full isolation of the out-of-order engine.
- Interrupt latencies are reduced thanks to fast interrupt prioritization logic.
- New memory protection features allow faster context switching.
- Enhanced bus fabric with quality of service capabilities prevents bus congestions.
- Caching has been optimized to ensure predictable instruction fetch and data access behaviors.
Together, these enhancements allow the Cortex-R52 to deliver scalable real-time performance while still providing isolation and deterministic behavior.
For safety-critical and high reliability systems, the Cortex-R52 includes a number of architectural features to improve fault resilience:
- Flexible lockstep configurations allow dual-core lockstep for fault detection.
- ECC support for both internal and external memories.
- Parity and error correcting code support in the core’s internal queues and data paths.
- Enhanced bus error reporting and recovery capabilities.
- Support for Arm’s Functional Safety architecture extensions.
These reliability and safety features enable the Cortex-R52 to more easily achieve safety certifications like ISO 26262 ASIL D in automotive applications.
The Cortex-R52 is aimed at computationally intensive real-time applications that need higher performance while maintaining predictability and reliability. Some examples include:
- Autonomous vehicles – sensor fusion, computer vision, path planning.
- Industrial automation and robotics – motion control, machine vision, predictive maintenance.
- 5G infrastructure – software defined networking and network functions virtualization.
- Aerospace and defense – radar processing, guidance systems.
The combination of power efficiency, real-time capabilities, safety features, and high performance makes the Cortex-R52 well suited for demanding embedded real-time workloads.
The Cortex-R52 implements the Armv8-R architecture with extensions for lockstep, virtualization, and functional safety. It is compatible with previous Armv8-R based Cortex-R processors from ARM and allows re-use of software investments on earlier R-series cores.
Cortex-R52 systems will require ARMv8 compatible operating systems or bare-metal firmware. Example RTOS options that support Armv8-R include FreeRTOS, Zephyr RTOS, Green Hills INTEGRITY, Mentor Nucleus RTOS, Wind River VxWorks, etc.
Toolchain support for Cortex-R52 requires ARM Compiler 6.16 or later. The core is also supported by GNU toolchains and other commercial toolchains implementing Armv8-R.
Licensing and Availability
As a design from ARM’s processor IP portfolio, the Cortex-R52 is available for licensing to ARM architecture licensees. Lead partners for the Cortex-R52 already include companies like NXP, Renault, Volkswagen, and NEC.
First silicon implementations of the Cortex-R52 are expected in late 2022 or early 2023. Broad availability of Cortex-R52 powered systems can be expected over the next few years as the core gets adopted across various embedded segments.
The Cortex-R52 continues ARM’s real-time computing roadmap by bringing substantially higher performance and efficiency while upholding the real-time capabilities and reliability needed for critical embedded workloads. As advanced workloads like AI/ML get deployed at the edge, the Cortex-R52’s scalable architectures provides an optimal blend of real-time responsiveness and computational throughput.