The WFI (Wait For Interrupt) and WFE (Wait For Event) instructions allow the Cortex-M3 processor to enter a low power state until a wakeup event occurs. This enables significant power savings in embedded systems through reducing dynamic power when the processor is idle.
Contents
- Introduction
- WFI Instruction
- WFE Instruction
- WFI vs WFE
- Use Cases
- Interaction with Peripherals
- Multicore Considerations
- Debug Considerations
- Wakeup Timing
- Testing Low Power Modes
- Tools for Analysis
- Conclusion
Introduction
Reducing power consumption is a key priority in many embedded systems, especially battery-powered devices. The Cortex-M3 CPU provides two instructions, WFI and WFE, to allow the processor to enter a low power state until a wakeup event occurs. This article provides a comprehensive guide on using these instructions to leverage the Cortex-M3 low power capabilities for reduced energy usage.
WFI Instruction
The WFI (Wait For Interrupt) instruction suspends execution on the CPU until an interrupt is received. This reduces dynamic power as the processor clock is gated during the low power state. WFI provides a light sleep mode with fast wakeup times.
Operation
When a WFI instruction is executed, the Cortex-M3 CPU core immediately enters the WFI low power state. This has the following effects:
- The core clock is gated off to prevent further execution. This eliminates dynamic power caused by unnecessary clocking.
- The processor maintains context including register contents. These are preserved so execution can resume transparently.
- Flash accelerators and debug logic remain active for fast interrupt response.
The CPU remains in WFI until a wakeup event occurs. This is triggered by a pending interrupt, or a debug event such as a breakpoint match. The core then exits WFI, the clock is re-enabled, and flow continues from the instruction after WFI.
Exiting WFI
The Cortex-M3 CPU exits WFI and wakes up on any of the following events:
- Interrupt – If an IRQ or FIQ interrupt becomes pending, the core re-enables clocks and exits WFI to service the interrupt.
- Reset – A system reset causes immediate wakeup from WFI.
- Debug Halting – Debug events such as breakpoints will also wake up the core.
When woken up, execution resumes from the instruction after WFI with all context maintained. The pending interrupt or debug event is then serviced.
Considerations
Key points to keep in mind when using WFI:
- Ensure interrupts are enabled before executing WFI. Otherwise the core cannot wake up.
- Use a debugger or analyzer to verify the core enters low power mode when expected.
- WFI only gates the core clock. Peripherals continue operating and consuming power.
- Wakeup time from WFI is fast, around 2 cycles of the core clock.
WFE Instruction
The WFE (Wait For Event) instruction suspends execution until a wakeup event is triggered by event hardware or a debugger. This provides a deeper sleep than WFI with slower wakeup times.
Operation
Executing a WFE instruction causes the Cortex-M3 CPU to enter the WFE low power state:
- The processor clock is gated off to halt execution and reduce dynamic power.
- Core state including registers is maintained.
- Wakeup logic blocks are put into a low power mode but remain powered on.
WFE has a lower power profile compared to WFI as wakeup logic is also power gated. However this increases wakeup latency.
Exiting WFE
The CPU exits WFE and resumes execution when either of these events occur:
- Event Signal – Hardware asserts the SEV or WFE wakeup event signal.
- Interrupt – A pending IRQ or FIQ will also wakeup the core from WFE.
- Reset – A system reset causes immediate WFE exit.
- Debug Halting – Breakpoints and watchpoint matches will wakeup WFE.
On wakeup, execution continues from the instruction after WFE. Any pending interrupts or debug events are then serviced.
Considerations
Key points to note when utilizing WFE:
- Ensure wakeup events from hardware peripherals or debug logic are enabled.
- Wakeup from WFE takes around 30 cycles of the core clock.
- WFE causes deeper power gating than WFI, peripherals should be prepared for this.
- Debug and profiling tools can help verify correct WFE behavior.
WFI vs WFE
The main differences between WFI and WFE low power modes are:
| Metric | WFI | WFE |
|---|---|---|
| Wakeup Sources | Interrupts, Resets, Debug | Interrupts, Resets, Debug, Event Signals |
| Power Reduction | Core clock gating only | Deeper power gating of CPU and wake logic |
| Wake Latency | ~2 clock cycles | ~30 clock cycles |
In summary, WFE provides lower power but higher wakeup latency compared to WFI. WFI is a lightweight mode with faster wakeup. The appropriate mode depends on power and performance needs of the application.
Use Cases
WFI and WFE have a variety of use cases in low power designs. Some examples include:
- Idle Processing – WFI can be used when the CPU is idle waiting for the next interrupt driven task.
- Peripheral Delay – WFE allows peripherals to wake the processor after completing tasks.
- Low Power Modes – Either instruction can integrate with power modes to reduce consumption.
- Wakeup Schedule – WFE enables scheduling periodic wakeups to handle background tasks.
- Sensor Hub – WFE allows fast wake on sensor data while processor sleeps.
Proper usage depends on the performance and power requirements of the system. WFI provides lower latency for interrupt-driven designs. WFE enables deeper power savings when longer wakeup delays are acceptable.
Interaction with Peripherals
When entering WFI or WFE, peripherals continue operating unaffected. However, there are some considerations when interfacing peripherals with low power modes:
- Check interrupts from peripherals can wakeup the processor as expected.
- Ensure peripherals contain context needed after wakeup, e.g. DMA descriptors.
- Verify peripherals function properly in the presence of clock gating or power gating.
- Some peripherals like GPIO may contain WFE wakeup event logic.
- Reference manuals provide details on integrating peripherals with low power modes.
Proper integration of peripherals is key to utilizing WFI/WFE while still maintaining required system operation. Testing should validate correct interaction with peripherals.
Multicore Considerations
Additional factors must be considered when using WFI/WFE with Cortex-M3 multicore systems:
- Each CPU core has independent WFI/WFE state and wakeup logic.
- Wakeup events should target specific cores to exit low power mode.
- Inter-processor interrupts allow one core to wake up another as needed.
- Shared resource access needs coordination if cores may wake asynchronously.
- Debuggers can wakeup or suspend individual cores independently.
With careful design, WFI and WFE provide benefits even for multicore Cortex-M3 implementations. Hardware coordination and inter-core communication enable optimized low power multi-processing.
Debug Considerations
Using WFI/WFE with debug tools such as JTAG requires some considerations:
- Debuggers can wakeup cores from WFI/WFE with breakpoints, watchpoints, etc.
- Enable debug logic such as breakpoint matches during low power modes.
- Debug power management settings may need adjustment.
- Verify debugger interfaces function properly in the presence of clock/power gating.
- Specialized low power debug features can enable non-invasive tracing.
With the right debug configuration, WFI/WFE power modes can be leveraged while still allowing robust debug capability. Debug power settings should be validated.
Wakeup Timing
It is important to characterize wakeup timing from WFI/WFE when verifying system performance:
- Wake latency depends on reset state, debug configuration, and pending events.
- Measure latency from event trigger to resumption of code execution.
- Ensure wakeup times match datasheet specifications and design requirements.
- Profile debug impact on wakeup latency if enabled.
- Optimize interrupt handling, debug logic, and peripherals to minimize delay.
Profiling tools can measure actual wakeup times during system operation. This data can guide optimization to meet timing requirements.
Testing Low Power Modes
Thorough testing is essential when using WFI/WFE to verify correct behavior:
- Inject interrupts and event signals to validate wakeup sources.
- Verify pending interruptswake up the processor as expected.
- Trigger debug halt events and validate low power exit.
- Insert instrumentation to measure wakeup latency.
- Validate peripheral and interconnect operation during and after low power states.
- Perform stress testing with continuous WFI/WFE cycling.
Both isolated testing and full system validation in end-use conditions are recommended when using WFI/WFE instructions. This can uncover any issues and ensure robust low power operation.
Tools for Analysis
Specialized tools help integrate and verify WFI/WFE low power modes:
- Logic Analyzers – Monitor CPU power states, wakeup signals, interrupt handling.
- Debug Probes – Halt and single-step through WFI/WFE execution.
- Power Profilers – Measure energy consumption in different use cases.
- Wakeup Latency – Profile timing from event to code execution.
- Bus Analysis – Validate peripheral access and DMA during low power states.
Proper tools give visibility into power state transitions, wakeup events, latency, peripheral operations, and other key metrics. They enable thorough validation and optimization of WFI/WFE low power designs.
Conclusion
The WFI and WFE instructions provide simple yet effective mechanisms to exploit the low power capabilities of the Cortex-M3 processor. By gating clocks and power domains, both instructions reduce dynamic power consumption during idle periods in application execution. WFI offers very fast wakeup at the expense of less power savings. WFE provides deeper power reduction through additional hardware gating but higher wakeup latency. Both instructions integrate seamlessly into interrupt-driven Cortex-M3 application firmware allowing optimized power efficiency without compromising performance.
Through careful design, configuration, debug, analysis, and validation, developers can leverage these instructions to significantly reduce energy usage. This enables longer battery life, cooler operation, and lower cost for a wide range of power-conscious Cortex-M3 based devices.
