Updating Board Files for Cortex-M0 DesignStart Eval r2p0 on MPS2+

The Cortex-M0 processor from ARM is an extremely popular 32-bit CPU optimized for low-power embedded applications. DesignStart Eval is a program from ARM that provides an easy and affordable way to evaluate Cortex-M0 on actual hardware, using the MPS2+ FPGA development board. The latest r2p0 release significantly improves upon the previous r1p0 version with bug fixes and new features. However, these updates require modifications to board support files in order to take full advantage.

Overview of Cortex-M0 DesignStart Eval r2p0

Some of the key improvements in the r2p0 release include:

• Compiler compatibility fixes for both gcc and ARM Compiler 6
• SWO trace support
• Standardised CMSIS interface
• Updated linker scripts and startup code
• Support for debugging with pyOCD/OpenOCD
• Miscellaneous bug fixes

With these updates, the Cortex-M0 DesignStart Eval program now provides an excellent starting point for evaluating the Cortex-M0 CPU and developing simple prototypes. However, the updates require changes to board support files like the linker script, startup code, and pin configurations.

Updating the Linker Script

The linker script provided with r2p0 is updated to support the full Cortex-M0 memory map. This includes regions for code, RAM, peripherals, and memory-mapped I/O. To take advantage of the new memory layout, the old linker script should be replaced with designstart-r2p0.ld from the release package.

Key updates include:

• Added Flash and RAM regions for code and data
• Reserved regions for peripherals and system registers
• Predefined output sections for easier code organization

With the new linker script, code and data can be placed appropriately to make full use of the Cortex-M0 memory architecture. The predefined output sections also make it easier to manage code flow and access to peripherals.

Updating the Startup Code

The r2p0 release also includes an updated startup file designstart-r2p0.s to initialize the processor and peripherals. The key changes are:

• Configuration of the Cortex-M0 system registers and core peripherals
• Initialization of the FPU if enabled
• Updated stack setup for ARM compiler 6
• Relocated interrupt vector table

With these enhancements to the startup code, the Cortex-M0reset configuration is standardized and matches the updated linker script memory layout. The file should directly replace any previous startup code versions.

Updating Pin Configurations

The r2p0 release shifts pin mappings and most peripherals are no longer enabled by default. To properly configure I/O pins and enable required peripherals, the mps2.h file provided with the release package should be used.

Key changes include:

• UART pins changed from P1_19/20 to P1_15/16
• I2C pins changed from P1_3/4 to P1_9/10
• SPI pins changed from P1_21/22/23 to P1_17/18/20
• Added macros to enable peripherals in Config Mode

The pin mapping changes impact any existing I/O code, so examples and drivers will need to be updated accordingly. The Config Mode macros enable control of which peripherals are initialized on startup.

Testing with Updated Board Files

Once the linker script, startup code, and pin configurations are updated per the r2p0 release package, basic functionality can be validated by compiling and running the blinky example.

Steps include:

1. Copy blinky.c and updated board files into a test project
2. Configure build tools to use designstart-r2p0.ld linker script
3. Compile blinky.c with designstart-r2p0.s startup code
4. Link with -specs=rdimon.specs and -lrdimon to enable debug
5. Load and run the blinky program on MPS2+ using OpenOCD/pyOCD

If LED blinks correctly, the build tools, pin mappings and startup sequence are configured properly. More comprehensive examples can then be compiled and debugged to continue Cortex-M0 evaluation.

Conclusion

Migrating to the updated board files in the Cortex-M0 DesignStart Eval r2p0 release requires changes to linker scripts, startup code, and pin configurations. With these simple updates, significant improvements are unlocked including proper memory layout, standardized configuration, and peripheral control.

After updating build tools and I/O mappings, basic functionality can be validated by compiling and running a simple blinky program. The enhanced evaluation board setup then provides a great starting point for further Cortex-M0 prototyping and development.