The Cortex-M0 processor from ARM is a popular 32-bit RISC core aimed at microcontroller and deeply embedded applications requiring low power consumption and design simplicity. The Cortex-M0 DesignStartTM program from ARM provides a pre-verified digital IP core which engineers can use to implement a Cortex-M0 based system-on-chip (SoC) design targeting FPGA or ASIC technology. When targeting an FPGA, the DesignStart Cortex-M0 core needs to be properly mapped to the specific FPGA architecture and device family being used.
FPGA Architecture Considerations
The key architectural aspects to consider when mapping a Cortex-M0 core to an FPGA include:
- Logic cells – The basic building blocks such as LUTs, flip-flops, and carry chains
- Block RAM – For data and instruction storage
- DSP slices – For arithmetic operations
- Clock management – PLLs, clock networks, global buffers
- Transceivers – High-speed serial I/O
- Hard processors – Processor cores pre-implemented in silicon
- Power management – Low power modes, power-saving options
The optimal mapping will efficiently utilize these various FPGA resources to meet the performance, cost, and power requirements of the target application. Tradeoffs are often required between throughput, logic utilization, memory bandwidth, clock speed, and power consumption.
Mapping to Xilinx FPGAs
For Xilinx FPGAs, the main device families to consider are:
- Spartan – Low-cost, entry-level FPGAs
- Artix – Low-power optimized FPGAs
- Kintex – Mainstream mid-range FPGAs
- Virtex – High-performance, high-capacity FPGAs
The Cortex-M0 core is well-suited for the smaller Spartan and Artix devices due to its modest resource requirements. The MicroBlaze soft processor core could also be used on these families but involves higher logic utilization. The larger Kintex and Virtex families enable much more complex SoC implementations.
Key Xilinx-specific features to leverage include:
- Block RAM for data and instruction storage
- DSP48 slices for hardware acceleration
- Clock management tiles for clock generation and distribution
- Power management options such as clock gating and low power modes
The Xilinx EDK and Vivado design tools provide a complete framework for implementing an embedded processor-centric SoC using IP cores like the Cortex-M0.
Mapping to Intel/Altera FPGAs
For Intel/Altera FPGAs, the Cyclone, Arria, and Stratix families are well-suited for Cortex-M0 based designs:
- Cyclone – Cost-optimized low-power FPGAs
- Arria – Mid-range FPGAs balancing cost and performance
- Stratix – High-performance FPGAs for bandwidth-intensive designs
Like with Xilinx devices, the Cortex-M0 is a good fit for lower cost Cyclone and Arria families, while Stratix would enable more advanced SoCs. The Nios II soft core could also be used but has higher resource usage.
Notable Intel/Altera features include:
- Tri-matrix embedded memory for data/instructions
- DSP blocks for hardware acceleration
- Clock management architecture for clock generation/distribution
- Power optimization through clock gating and low power modes
The Intel/Altera Quartus Prime design software delivers a complete environment for crafting SoCs integrating the Cortex-M0 core.
Mapping to Lattice FPGAs
For Lattice Semiconductor FPGAs, the primary device families include:
- iCE40 – Ultra-low-power FPGAs
- ECP5 – Low-cost FPGAs balancing power and performance
The low-power iCE40 devices are a good fit for simple Cortex-M0 microcontroller designs. The more capable ECP5 family enables higher performance Cortex-M0 based SoCs. Lattice’s soft FPGA cores could also be used.
Key Lattice features for Cortex-M0 integration include:
- Embedded block RAM for data and instructions
- PLLs for clock generation
- Power reduction through clock gating and power modes
The Lattice Radiant and Radiant 2 design software provides the tools to implement Cortex-M0 designs targeting Lattice FPGAs.
Mapping to Microsemi FPGAs
For Microsemi FPGAs, the IGLOO2, ProASIC3 and SmartFusion2 families are relevant for Cortex-M0 integration:
- IGLOO2 – Low-power mixed-signal FPGAs
- ProASIC3 – Low-cost FPGAs
- SmartFusion2 – Mixed-signal FPGAs with ARM cores
IGLOO2 and ProASIC3 devices allow implementing low-cost Cortex-M0 based solutions. SmartFusion2 includes an embedded Cortex-M3 which can be used instead of the Cortex-M0 soft core.
Microsemi FPGA capabilities include:
- Embedded flash memory for data/instructions
- ADC/DAC support on mixed-signal FPGAs
- Clock conditioners for clock generation/distribution
- Low power modes through clock gating and power shutoff
The Microsemi Libero SoC design suite enables crafting SoC solutions with the Cortex-M0 core targeting Microsemi FPGAs.
Mapping to QuickLogic FPGAs
For QuickLogic FPGAs, the EOS and PolarPro families are suitable for Cortex-M0 integration:
- EOS – Ultra-low-power sensor processing FPGAs
- PolarPro – Low-power mid-range FPGAs
The low-cost, low-power EOS family is ideal for simple embedded applications built around the Cortex-M0. The more advanced PolarPro devices enable higher performance SoC implementations.
QuickLogic’s key capabilities include:
- Embedded SRAM for data/instructions
- Low-power programmable fabric architecture
- Flexible clock management architecture
The QuickLogic design software facilitates embedding the Cortex-M0 into low-power solutions targeting QuickLogic FPGAs.
Conclusion
Successfully mapping the Cortex-M0 processor core to an FPGA requires understanding the target device architecture and utilizing key hardware resources and design tools. With FPGAs from vendors like Xilinx, Intel/Altera, Lattice, Microsemi and QuickLogic, the Cortex-M0 DesignStart IP can be tailored to meet the needs of a wide variety of embedded systems and IoT applications requiring an energy-efficient 32-bit processor.
