The Cortex-M0 processor from ARM is one of the most popular 32-bit microcontroller cores on the market today. As one of the smallest ARM cores available, it is well-suited for embedded applications requiring low cost and power consumption. The DesignStart program from ARM provides a simplified and pre-verified Cortex-M0 core to enable rapid prototyping and development. When paired with the Xilinx ISE design suite, designers can take the Cortex-M0 from concept to implemented design quickly and efficiently.
Introduction to the Cortex-M0 DesignStart Core
The Cortex-M0 DesignStart core contains just the essential logic required to implement a basic Cortex-M0 CPU. This includes the CPU, nested vectored interrupt controller, sysTick timer, bus interfaces like AHB-Lite and APB, and debug components. Notably absent are peripherals, memory interfaces, and clock/reset control logic. The DesignStart core is provided as synthesizable RTL targeting implementation in low-cost FPGAs and CPLDs.
Some key features of the DesignStart Cortex-M0 core:
- 32-bit ARM Cortex-M0 processor
- Up to 50 MHz operating frequency
- AHB-Lite and APB interfaces
- Nested Vectored Interrupt Controller
- Low gate count – Approximately 12k gates
- Suitable for low-cost FPGAs & CPLDs
The absence of peripherals and interfaces provides flexibility for designers to customize the system while minimizing unnecessary logic. Overall, the DesignStart program enables rapid prototyping of a Cortex-M0 system with minimal upfront cost or licensing fees.
Acquiring the Cortex-M0 DesignStart Core
To begin a Cortex-M0 DesignStart project, designers must first obtain the RTL code from ARM. This requires signing up for a free ARM account and agreeing to the DesignStart Eval license terms. The license provides access to the full DesignStart RTL deliverables for evaluation and prototyping purposes.
The DesignStart package includes everything required to implement the core in a FPGA or CPLD:
- Synthesizable VHDL and Verilog RTL source code
- Integrated testbenches and simulation scripts
- Documentation and implementation notes
- Example RTL subsystems
No license fees or royalties are required when prototyping the DesignStart core. However, a full Cortex-M0 license must be obtained from ARM or a distributor to take a design to production.
Installing Xilinx ISE Design Suite
Xilinx ISE provides a complete FPGA design suite including synthesis, place and route, and verification tools. A free WebPack version can be downloaded from Xilinx after registration. The ISE tools run on Windows or Linux workstations.
Key steps for installing ISE WebPack:
- Download the ISE installer executable from Xilinx
- Run the installer and follow the prompts to install ISE and select components
- Activate the license if necessary
- Install service packs and patches if available
The core ISE tools include:
- XST – Synthesis tool
- NGDBuild – Translate HDL to netlist
- MAP – Map to FPGA resources
- PAR – Place and route design
- TRCE – Timing analysis
- XFLOW – Automation and scripting
Additional utilities are available like the ChipScope debug core inserter. Make sure the FPGA device family required for the project is supported by the ISE version.
Configuring an ISE Project
ISE organizes design sources and results into projects. After installing ISE, a new project can be created with the New Project Wizard. The key steps are:
- Name project and specify directory location
- Add RTL design sources
- Specify top-level module
- Select target FPGA device
- Select device package and speed grade
- Specify project properties and settings
For the Cortex-M0 project, the DesignStart RTL and testbench files should be imported. The top-level module will be the cortexm0_integration.v file. Selecting the appropriate FPGA device is important, as the Cortex-M0 requires about 12,000 gates. Low-cost devices like Spartan-6 or older Spartan-3 series are likely suitable.
Critical project settings include:
- Default compilation tool – Select VHDL or Verilog compiler
- HDL source file type assertion – VHDL or Verilog
- Default options for compilation
The ISE project will now contain all source files required to synthesize the Cortex-M0 core.
Simulating the Design
Before attempting synthesis, the DesignStart RTL code should be simulated to verify correct functionality. The ARM-provided testbenches and simulation scripts can be used for this purpose.
To run simulation:
- Add simulation sources to project
- Select top-level simulation module
- Choose simulator (ISim or ModelSim)
- Run simulation script
ISim provides basic simulation capabilities and integrates directly with ISE. ModelSim requires a license but provides more advanced debugging features.
The testbenches will apply stimulus like clock signals, resets, and bus transactions while monitoring DUT outputs. Simulation results should match expected behavior to increase confidence in synthesis results.
Synthesizing the Design
With confidence in the RTL functionality from simulation, the Cortex-M0 core can now be synthesized to target the selected FPGA architecture. Synthesis converts the RTL code into a gate level netlist mapped to FPGA logic blocks and routing.
To run synthesis:
- Select “Synthesize – XST” in ISE processes
- Verify design analysis reads successfully
- Review reports after synthesis completes
- Check for timing constraints met
- Iterate to meet requirements if needed
The main synthesis reports to review are:
- Synthesis report – Primary resource usage summary
- RTL schematic – Visual block representation
- Timing report – Detailed timing analysis
Key metrics to validate are number of occupied slices, frequency timing closure, and matching resource totals estimated by ARM. If synthesis is successful, a gate level netlist will be generated.
Implementing the Cortex-M0 in the FPGA
With a functionally verified netlist, the next step is transforming and mapping the abstract netlist into the physical FPGA resources through place and route. This phase will create a Bitstream file to configure the FPGA with the Cortex-M0 implementation.
To implement the design:
- Run “Generate Programming File” process
- Select steps for NGDBuild, MAP, PAR, and Bitgen
- Review implementation reports
Especially important is analyzing the timing reports after place and route to validate timing closure. If maximum frequency requirements are not met, constraints may need adjustment or synthesis re-run to meet timing.
The end result is a Bitstream file containing the programmer data to load the Cortex-M0 core into the FPGA. This can be downloaded to the physical FPGA board to realize the DesignStart processor.
Next Steps with the Cortex-M0 Core
At this point the designer has a verified and implemented Cortex-M0 CPU targeting a low-cost FPGA development board. The core itself is not functional until interfaced with memories, peripherals, and interrupts.
To create a complete Cortex-M0 system on the FPGA:
- Add FPGA-hosted memories for code storage and data
- Interface board I/O to create necessary peripherals
- Connect interrupts from internal or external sources
- Develop software stack including C runtime and drivers
With this infrastructure in place, custom embedded software applications can be created to run on the processing system.
ARM provides a number of online resources to assist with integrating and developing with the DesignStart Cortex-M0 core:
- DesignStart community forums
- Example subsystem reference designs
- Cortex-M0 user guides and application notes
- mbed OS for rapid software development
In summary, by leveraging the simplified DesignStart Cortex-M0 in Xilinx’s ISE tools, embedded designers can quickly prototype and evaluate ARM’s incredibly popular Cortex-M class of processors at no upfront cost before taking a design into full production.