The Cortex-M1 processor from ARM is designed for microcontroller applications and features a stripped down version of the ARMv6 instruction set. Initializing and accessing different types of memories is key to utilizing the Cortex-M1 effectively in embedded systems. This article provides an overview of the different memory types supported by Cortex-M1 and how to initialize and access them from software.
The Cortex-M1 processor contains small amounts of on-chip SRAM and ROM memories to hold code and data. These memories are mapped into the processor’s memory map and can be accessed directly without any initialization.
The SRAM is volatile memory used to hold both code and data. It is small in size, usually between 16-64KB. The SRAM memory is mapped starting from address 0x00000000 in the processor’s memory map. It can be read and written by the processor directly using load/store instructions. No initialization is required to access the SRAM.
The ROM is non-volatile memory containing boot code. It is mapped starting from address 0x00002000 in the memory map. The ROM can only be read by the processor and is used to hold important code like interrupt vectors and boot startup routines. No initialization is required to access the ROM contents.
Since the on-chip memories are very small, external memory interfaces are used to connect to larger memories like flash and RAM. Common memory interfaces supported by Cortex-M1 include external bus interface and external memory interface.
External Bus Interface
The external bus interface (EBI) allows connection to external memories like flash, SRAM, and even displays. It provides a multiplexed address and data bus that can be connected to various external memory and peripheral chips.
To use the EBI, the desired external memories need to be first mapped to an address range in the processor’s memory map. This is done by configuring the Memory Mapping Unit (MMU) registers to set the start address and size for each external memory region.
For example, to map an external 16MB flash chip, the MMU start address register can be set to 0x60000000 and the size to 16MB or 0x01000000. This will map the external flash from 0x60000000 to 0x6FFFFFFF in the memory map.
In addition to mapping, the external memory devices also need to be configured correctly using their control signals. For example, flash memory may require specific sequencer configuration and timing. All these external memory details are configured through the EBI registers in the Cortex-M1.
Once mapped and configured correctly, the external memories can be accessed just like internal SRAM using load/store instructions. The processor will automatically interface with the external memory device correctly based on the EBI configuration.
External Memory Interface
The External Memory Interface (EMI) is used to interface with external memories like SRAM, SDRAM, etc. It provides a dedicated data and address bus with support for advanced capabilities like burst access and memory interleaving.
Similar to EBI, the external memory first needs to be mapped into the processor’s memory map using MMU configuration. EMI specific registers are then used to configure the memory timing and capabilities.
For example, to use a 16-bit external SRAM, the EMI data bus width register can be set to 16-bits. Other parameters like read and write timings, wait states, and memory regions are also configured.
Once properly configured, the external memory can be accessed seamlessly using load/store instructions, and the EMI hardware handles all the protocol and timing requirements transparently.
Here are some tips on accessing different memory types from Cortex-M1:
- Use normal load/store instructions to access on-chip SRAM/ROM. No special handling needed.
- Ensure MMU mappings and configurations are done before accessing any external memory.
- Try to maximize sequential accesses and minimize random accesses for better performance.
- Use caching if available to reduce average access time.
- Avoid overlapping external memory regions in the MMU configuration.
- Use dedicated stack/heap memory regions separate from code to avoid collisions.
- Keep track of which memory regions are for what purpose in your application.
- Use memory barriers and cache control instructions when dealing with shared memory.
Here is an example initializing external 16MB flash memory connected over EBI: // Enable MMU and set page size MMU_CTRL = 0x01; MMU_PAGE_SIZE = 0x00000800; // Map external flash from 0x60000000 to 0x6FFFFFFF MMU_FLASH_START_ADDR = 0x60000000; MMU_FLASH_END_ADDR = 0x6FFFFFFF; // Configure external bus timing for flash EBI_CS_FLASH_SETUP_CYCLES = 0x05; EBI_CS_FLASH_HOLD_CYCLES = 0x03; // Enable EBI control signals for flash EBI_CS_FLASH_ENABLE = 0x01; EBI_CS_FLASH_POLARITY = 0x00; // Now external flash can be accessed from 0x60000000!
This covers the basics of initializing and accessing different memory types with the Cortex-M1 processor. The memory architecture can be customized and optimized based on the system requirements. Proper configuration is essential to managing on-chip and external memories correctly. With a well configured memory system, the Cortex-M1 can access code and data seamlessly to enable powerful embedded applications.