The JTAG-DP and SWJ-DP are two commonly used debug ports for ARM Cortex-M series microcontrollers. Both provide debug access and programming capabilities, but have some key differences.
Overview of JTAG-DP and SWJ-DP
JTAG-DP refers to the JTAG Debug Port, which utilizes the IEEE 1149.1 JTAG interface standard. It provides 4 pins for debug access – TCK, TMS, TDI, and TDO. TCK is the clock pin, TMS is the mode select pin, TDI is the test data in pin, and TDO is the test data out pin.
SWJ-DP refers to the Serial Wire JTAG Debug Port. It combines JTAG and SWD (Serial Wire Debug) interfaces over just 2 pins – SWCLK and SWDIO. SWCLK is the clock pin, while SWDIO handles bidirectional data transfer.
Both JTAG-DP and SWJ-DP allow debuggers to access the Cortex-M core registers, set breakpoints, download code, and control execution. But there are some important aspects that differentiate the two debug ports.
Key Differences
Number of Pins
The most obvious difference is the pin count. JTAG-DP requires 4 dedicated pins on the MCU, while SWJ-DP needs only 2 pins. This makes SWJ-DP more pin-efficient.
Speed
SWJ-DP is significantly faster compared to JTAG-DP. JTAG-DP has a maximum clock speed of around 5-10 MHz, while SWJ-DP can go up to 30 MHz. This is because SWD protocol is simpler and more efficient than JTAG.
JTAG Compatibility
JTAG-DP is fully compatible with IEEE 1149.1 JTAG. It supports all JTAG instructions like EXTEST, INTEST, BYPASS etc. SWJ-DP does not support the complete JTAG instruction set, but only provides debug features over the SWD protocol.
Interface Complexity
JTAG requires coordinating the TMS mode select signals along with the TCK clock to control the TAP controller state machine. SWD does away with this complexity by using simpler point-to-point data transfers.
Support for Boundary Scan Testing
A key feature of JTAG is its support for boundary scan testing using the EXTEST instruction. This allows testing interconnections between devices on a PCB. SWJ-DP does not support boundary scan testing features of JTAG.
Ability to Chain Multiple Devices
JTAG allows chaining together multiple devices using the TDI and TDO connections. This allows testing multiple devices over the same JTAG port. Chaining is not possible with the SWJ-DP interface.
Use of Trst Pin
JTAG uses an optional Trst (Test Reset) pin to reset the TAP controller and force it into the Test Logic Reset state. SWJ-DP does not have a Trst pin.
Cortex-M Debug Port Configuration Options
ARM Cortex-M microcontrollers can be configured with different debug port options:
- JTAG-DP only
- SWJ-DP only
- Combined JTAG-DP and SWJ-DP
- No debug port enabled
Having both JTAG-DP and SWJ-DP allows leveraging the benefits of both interfaces. JTAG-DP provides full JTAG compatibility and boundary scan testing capability. SWJ-DP offers faster debug speed and fewer pins.
Debug Access Mechanism
Both JTAG-DP and SWJ-DP work by providing access to the Cortex-M Debug Access Port (DAP). This allows communicating with the Debug Access Port using either the JTAG protocol or the SWD protocol.
The Debug Port provides access to the following key resources:
- Debug Control Block (DCB) – Used to configure debug features and access debug components like watchpoints.
- Access Port Registers – Provide debug status information and configuration options.
- Instrumentation Trace Macrocell (ITM) – Enables trace data output for debugging.
- Embedded Trace Macrocell (ETM) – Provides instruction and data tracing capabilities.
- Cross Trigger Interface (CTI) – Allows triggering events across multiple cores.
- Trace Port Interface Unit (TPIU) – Manages outbound trace data transfers.
The key benefit of both JTAG-DP and SWJ-DP is that they enable reading and writing all Core registers in the Cortex-M processor using debug instructions. This provides complete view and control over the processor state during debugging.
JTAG vs SWD Protocols
Both JTAG-DP and SWJ-DP use different protocols to communicate with the Debug Access Port.
JTAG Protocol
JTAG uses four to five signals – TCK, TMS, TDI, TDO and optionally Trst. The TAP controller state machine controls the JTAG sequence. Data is shifted serially bit-by-bit into the instruction register and data registers.
JTAG supports both high-speed data transfer and low-speed control interactions. Two handshaking mechanisms are defined – host to target handshaking for low-speed transfers, and target to host handshaking for high-speed transfers.
SWD Protocol
Serial Wire Debug uses just two wires SWCLK and SWDIO for bidirectional data transfer. The SWDIO line doubles up for both control and data transfer.
SWD does not use any state machine and has a much simpler point-to-point transaction based protocol. Packets are sent containing the request destination address, data, parity, and turnaround. The ACK response provides flow control.
SWD supports only high-speed data transfers, with no low-speed option. The simpler protocol offers higher throughput compared to JTAG.
Debug Probe Hardware
To access the Cortex-M debug ports, a debug probe hardware is required. This may be a standalone probe like Segger J-Link, ULINKplus, etc. Or on-chip debug logic like CoreSight DAP. Debug probes generally support both JTAG and SWD and can automatically detect the enabled debug port.
For best results, probes like J-Link provide ultra high speed data transfer using technologies like JTAG over Clock-Data-Recovery (CDR). This can clock JTAG-DP up to around 90 MHz, approaching SWD-DP maximum speeds.
Software Debugger Host Tools
Host debugger tools connect to the debug probe hardware to access the target Cortex-M system. Examples include Eclipse, SEGGER Ozone, Keil MDK, IAR EWARM, etc.
These tools allow viewing and modifying registers, downloading code, setting breakpoints, and other debugging tasks. The debugger abstracts details of the access protocol, providing a unified interface for both JTAG-DP and SWJ-DP.
Summary and Recommendations
In summary, the key differences between JTAG-DP and SWJ-DP are:
- JTAG-DP requires 4 pins versus 2 pins for SWJ-DP
- SWJ-DP offers faster debug speeds of up to 30 MHz versus 10MHz for JTAG-DP
- Only JTAG-DP provides full JTAG compatibility and boundary scan support
- SWJ-DP has a simpler interface and protocol compared to JTAG
The recommended approach is to enable both JTAG-DP and SWJ-DP in Cortex-M designs. This allows you to leverage the benefits of both interfaces:
- Use SWJ-DP for faster debug access during active debugging sessions
- Use JTAG-DP for board-level testing and firmware updates where speed is not critical
- boundary scans are required
For best performance, invest in a high-speed debug probe hardware like Segger J-Link that can maximize JTAG-DP and SWJ-DP speeds. On the software side, use a debugger tool that provides an intuitive and consistent interface for both JTAG-DP and SWJ-DP access.
