The Cortex-M3 processor offers a deep sleep mode that allows the system to enter an extremely low power state while retaining the contents of RAM. This allows maximum power savings while still providing fast wake-up times. Utilizing deep sleep mode properly is key to optimizing battery life in Cortex-M3 based devices.
Introduction to Deep Sleep Mode
Deep sleep mode, also known as power-down mode, is a low power mode where the Cortex-M3 core, peripherals, and memory system are powered down. Only the Always-On (AON) power domain remains powered on to keep vital functions alive. The AON domain includes the AON block with power supervisor, 64kB AON SRAM, watchdog timers, and low power clocking.
In deep sleep mode, RAM contents are preserved. This allows the system to resume execution quickly after waking up since RAM initialization is not needed. However, core, peripheral, and clock registers need to be restored. Flash memory also remains powered on in deep sleep mode to allow fast wake-up.
To enter deep sleep mode, the WAIT_FOR_INTERRUPT (WFI) instruction is executed after setting the SLEEPDEEP bit in the System Control Register (SCR). This will cause the processor to enter deep sleep mode and remain there until an interrupt or reset occurs to exit deep sleep mode.
Power Savings in Deep Sleep Mode
Deep sleep mode allows extensive power savings as power domains are shut down completely. The Cortex-M3 core consumes only around 10% of its regular operating power in deep sleep mode. RAM consumes 5-10% of operating power. Flash consumes less than 1% of operating power.
Overall system power can be under 50uA in deep sleep mode, compared to around 10mA in active mode for a typical system running at 20MHz. This represents power savings of 200x or more. Exact power numbers depend on the specific chip and system configuration.
Peripheral power consumption is also minimized in deep sleep mode. Analog peripherals such as ADC, comparators, and voltage reference can be shut down. Digital peripherals consume close to zero power when their clocks are gated in deep sleep mode.
Wake Up from Deep Sleep Mode
The processor can be woken up from deep sleep mode by any enabled wake-up source. Typical wake-up sources include:
- External interrupt from GPIO pin
- Watchdog timer interrupt
- Low power timer interrupt
- External reset signal
When a wake-up event occurs, the system will exit deep sleep mode and resume execution based on the interrupt handler or reset sequence. Program execution resumes from the WFI instruction that was used to enter deep sleep mode.
Since RAM is preserved and flash remains on, normal program execution can resume quickly after wake-up without the need for re-initialization in most cases. Startup time from deep sleep is usually much faster than cold boot time.
Deep Sleep Mode Configuration
Proper configuration is required to make effective use of deep sleep power savings. Here are some key steps for configuring deep sleep mode:
- Enable SLEEPDEEP mode in SCR sleep control register
- Configure SYSCLKCTRL clock control register for low power clocking
- Gate clocks for unused peripherals using peripheral clock control registers
- Minimize PLL power during deep sleep by disabling or reducing clock frequency
- Configure analog peripherals such as ADC and comparators for disabled or low power state
- Use AON timers if timing or watchdog functions are needed in deep sleep
- Manage wake-up sources by enabling and prioritizing interrupts
- Set up system restore mechanism to recover after wake-up
In addition, program code should be structured properly to utilize deep sleep efficiently:
- Execute WFI instruction to enter deep sleep mode when idle
- Use wake-up interrupts to trigger tasks and re-enter low power modes
- Minimize unnecessary activity before re-entering low power modes
Optimizing Wake-Up Time
While deep sleep mode saves significant power, a key metric is how quickly the system can wake up and become operational. Wake-up time depends on:
- Interrupt latency – time from interrupt detected to handler executed
- Clock stabilization – time for clocks to start and stabilize
- Restore delay – time to recover peripheral registers, memory, etc
Interrupt latency can be minimized by using fast wake-up sources like GPIO pins. Nested vectored interrupt controller (NVIC) should be configured for low latency. Clock trees should be optimized for fast start up and PLL settling.
Custom restore sequences can be implemented to recover system state optimally after wake-up. Power critical applications may require wakeup times under 10 microseconds.
Real-Time Clock Configuration
To maintain accurate timekeeping in deep sleep mode, a real time clock (RTC) peripheral is extremely useful. The RTC can keep time with very low power using a separate power domain.
The RTC should have a 32.768kHz clock source that stays running in deep sleep mode. RTC registers can be used to set timekeeping and timestamp events during deep sleep. When waking up, the core can read the RTC time to maintain accurate system time.
RTC peripherals may offer alarms, counters, and timestamp capabilities to trigger timed wake-ups from deep sleep. RTC events can eliminate the need for higher power timers in deep sleep mode.
Debugging in Deep Sleep Mode
Debugging sleep related issues can be challenging. Debug modes will override low power modes and keep the processor powered on. To observe true deep sleep behavior, debugging should be minimized.
However, limited use of debugger features like breakpoints and step execution can aid in verifying correct transition into and out of deep sleep modes. The debugger can show register states before and after low power modes to ensure proper configuration.
Debug power modes can also force the processor into deep sleep artificially even with debug attached. This allows testing deep sleep wake-up logic without actually having to wait for the full deep sleep time durations.
Use Cases for Deep Sleep Mode
Here are some common use cases where deep sleep mode provides significant benefit:
- Battery operated devices – Deep sleep maximizes battery life for portables and wearables.
- Periodic monitoring – System sleeps between sensor measurements to conserve power.
- Real time clocks – Deep sleep maintains timekeeping at very low power.
- Wireless sensor nodes – Nodes remain in deep sleep most of the time, waking only to transmit.
Deep sleep mode balances the need for low active power consumption and fast wake-up time in battery operated devices. Designers can leverage the flexibility of deep sleep configuration options to optimize for a particular use case.
Conclusion
The Cortex-M3 deep sleep mode enables significant power reductions, allowing even battery operated devices to achieve years of operable time. With proper configuration of clocking, peripherals, interrupts, RTC, and code, deep sleep current can reach extremely low levels in the microamp range.
At the same time, wake-up latency from deep sleep mode can be very quick thanks to retained RAM and flash context. Fast wake-up response time allows more aggressive use of deep sleeps during idle periods. Optimizing deep sleep mode usage is key to maximizing battery life in wearables, sensors, monitors, and other space/power constrained devices.
