The Cortex-M3 processor from ARM offers various sleep modes that can be leveraged for power management. By utilizing the sleep modes effectively, significant power savings can be achieved in Cortex-M3 based systems.
Overview of Cortex-M3 Sleep Modes
The Cortex-M3 processor supports three main sleep modes:
- Sleep mode
- Deep sleep mode
- Standby mode
In sleep mode, the core, memories, and peripherals remain powered on. The processor clock is gated off to reduce dynamic power dissipation. Wake up from sleep mode is very fast since the processor state is maintained.
In deep sleep mode, the core, peripherals, and SRAM memories are powered off. Only wake up logic like interrupt controllers remain powered on. Since processor state is lost, wake up is slower than sleep mode. Dynamic and static power consumption are minimized.
Standby mode provides the lowest power consumption. The entire Cortex-M3 system including all memories and logic is powered off. Only basic wake up logic remains powered on. A full system restart is required to resume operation after standby. Wake up time is consequently the longest.
Sleep Mode Configuration
Using the Cortex-M3 System Control Block (SCB), sleep modes can be easily configured. The SCB includes a Sleep and Deep Sleep Control register that is used to select the desired low power mode. Setting this register puts the processor into sleep or deep sleep mode immediately.
For example, to put the Cortex-M3 into sleep mode, the SLEEPDEEP bit in the register is cleared. For deep sleep mode, SLEEPDEEP is set to 1. Standby mode is entered by asserting a standby input pin signal.
In addition, interrupt sources can be enabled to wake up the processor from sleep and deep sleep modes using the SCB System Handler Control and State register. This allows flexible wake up triggering through external or internal interrupt events.
Power Management with Sleep Modes
Effective usage of the Cortex-M3 sleep modes involves determining optimal times to enter each low power state. Tradeoffs between wake up time, power savings, and interrupt latency need to be balanced as per application requirements.
For example, in an application that involves sporadic external events, sleep mode should be used. Since peripheral and memory state is maintained, interrupt handlers can immediately service events with low latency. Dynamic clock gating provides decent power savings while keeping wake up delay minimal.
For periodic data acquisition type applications, deep sleep mode with RAM retention provides a good balance. SRAM memory contents are preserved so that context is not completely lost. Wake up delays are still reasonably fast. Power consumption is substantially reduced though both dynamic and static currents.
Standby mode works best in systems that have long idle periods between activities. All device state is lost, so the application must reinitialize after wake up. This allows maximum power reduction during extended idle events. Wake up time can be unpredictable depending on the root cause of the reset.
In devices that need a very fast response to random external or internal events, sleep would be preferred over deep sleep. In cost sensitive devices that can tolerate some idle time, deep sleep offers better power savings. Standby mode provides the highest power reduction for devices that are idle for longer durations.
Wake Up Event Configuration
For reliable wake up from sleep and deep sleep modes, interrupt sources need to be properly configured. This involves enabling interrupts in the NVIC interrupt controller as well as configuring options like edge triggered or level triggered in the Cortex-M3 interrupt lines.
For example, to wake up on an external GPIO pin event, the corresponding GPIO and external interrupt lines must have interrupts enabled in the NVIC. The pin should be configured for edge triggered interrupts. Similar considerations apply for internal peripheral events like ADC conversion completions and timers.
In some cases, multiple wake up sources may be required. The SCB System Handler Control and State register allows any combination of interrupts to be set as wake up events through configuration of the IRQ and FIQ interrupt enables.
Unwanted or spurious wake ups can be minimized by disabling unused interrupt sources explicitly. Proper priority settings and interrupt handler code also helps avoid inadvertent wake ups in complex applications.
Low Power Software Coding Practices
In addition to the hardware based sleep mode configuration, software techniques can maximize power reduction. Keeping the Cortex-M3 in sleep or deep sleep modes for longer durations allows minimizing dynamic current consumption.
This requires ensuring that execution quickly enters the low power mode once tasks are completed. Any unnecessary delays or waiting in loops will prevent entering sleep/deep sleep.
Interrupt driven designs work well to allow quick re-entry into sleep after handler execution. Handler code must be optimized to avoid delays. Using Direct Memory Access (DMA) transfers also allows data movement without wasting cycles.
Peripheral behavior must be analyzed to see if any unnecessary activity can be disabled when idle. For example, disabling a running ADC during idle periods avoids excessive sampling.
Code execution from RAM rather than flash allows minimizing memory current draw. Flash can be kept off in deep sleep mode. For very low power standby mode, RAM retention can also be disabled to save leakage currents.
With careful low power aware software design complementing the hardware sleep modes, Cortex-M3 current consumption can be optimized for many embedded system applications.
Wake Up Timing
An important consideration when using sleep and deep sleep modes is the wake up timing. This determines how quickly the Cortex-M3 can respond to external or internal events that cause interrupts and exit low power mode.
In sleep mode, wake up time is very fast at around 10 microseconds typically. Only the clocks need to restart and the processor can immediately resume execution. Performance impact is negligible.
For deep sleep mode, wake up time is longer and depends on the memory, peripherals, and I/O configuration. With flash memory active, the wake up time can be around 100 microseconds. Disabling flash memory reduces this to 10 microseconds.
Wake up time is also influenced by running I/O pins at higher frequencies. Light loading allows faster recovery. Loading pins heavily can increase deep sleep wake up time to microseconds. So deep sleep is best used in applications that do not require very fast random interrupt response.
Wake up from standby mode is the slowest, ranging from milliseconds to seconds. A full system restart is required to recover from standby. So this mode is suited for infrequent events ortoggle operation.
Power Consumption Numbers
To quantify the benefits of the Cortex-M3 sleep modes, typical power consumption numbers are listed below as a reference:
- Active mode: Around 230 A/MHz
- Sleep mode: 130 A/MHz (44% reduction)
- Deep Sleep, RAM ON: 21 A/MHz (91% reduction)
- Deep Sleep, RAM OFF: 2.1 A/MHz (99% reduction)
- Standby mode: 1 A (99.9% reduction)
These numbers will vary based on exact MCU configuration and application details. But the savings from deep sleep and standby modes are considerable through both dynamic and static power reduction.
For example, during long idle periods of a second, over 200 mA of active current consumption can be reduced down to the A range in deep sleep/standby. This highlights the importance of utilizing the sleep modes effectively.
Peripheral State Retention
In deep sleep mode, Cortex-M3 peripherals like GPIO, timers, serial, ADC etc are powered down and lose state. This may be acceptable for some applications.
However in other cases, retaining peripheral state in deep sleep can be advantageous. For example, preserving timer count values across sleep prevents time loss. Maintaining UART configuration avoids reconfiguring after wake up.
The Cortex-M3 allows flexible peripheral state retention options in deep sleep mode through the PCONP register. Individual peripherals like ADC, timers, watchdog etc can be enabled to keep state. This allows optimizing deep sleep current while maintaining necessary peripheral context.
Peripheral state retention does increase deep sleep current marginally. So only necessary peripherals should have state retention enabled. For example, if only the watchdog needs to run in deep sleep, other peripherals can be safely powered down.
Sleep Walking for Real Time Response
Sleep walking is an advanced technique that allows real time response to continue even in deep sleep mode. Essential interrupt handlers run as normal while non-essential handlers are blocked.
This avoids wake up for every interrupt. The Cortex-M3 sleep walking feature improves real time response dramatically compared to legacy sleep modes. Power consumption also reduces through avoiding unnecessary wake ups.
Sleep walking works by separating interrupts into privileged and non-privileged. Only privileged interrupts are serviced transparently in sleep mode. Attempts to execute non-privileged handlers cause wake up first.
So key real time application handlers can be set as privileged to respond immediately. Non critical handlers are set to non-privileged and allowed to trigger just wake up. This ensures real time behavior without sacrificing power reduction.
The Cortex-M3 CONFIG_SLEEPF Walking Enable bit enables this mode. Individual interrupts are marked privileged or non-privileged through the NVIC. So sleep walking provides both power and real time improvements.
Low Power Mode Usage Examples
Here are some example usage scenarios for the Cortex-M3 low power modes:
- Wireless Sensor: Sleep mode used to gate clocks during idle. Wake up on RF interrupts for low latency packet handling.
- Voice Recorder: Deep sleep used between user interactions. Fast wake up on touch input.
- Smart Lock: Standby mode when unlocked and inactive. Wake up on lock/unlock events.
- Remote Control: Sleep walking for real time response. Deep sleep otherwise to maximize battery life.
In this way, the optimal low power mode can be selected based on allowable wake up time, interrupt latency, power constraints, and real time requirements.
Conclusion
The Cortex-M3 sleep modes provide flexible options for power management. Sleep mode offers the fastest wake up and response for real time constraints. Deep sleep further reduces power for periodic events. Standby mode maximizes reduction for infrequent activity.
Utilizing these sleep modes effectively requires analyzing application requirements. Wake up time, peripheral state retention, and interrupt response latency should guide mode selection. With intelligent low power software design, the Cortex-M3 sleep modes enable optimized power consumption in IoT edge devices.
