The ARM Cortex-M4 is a 32-bit processor core used in various microcontroller units (MCUs) and system-on-chips (SoCs). It has a sophisticated memory architecture that provides flexible options for mapping code, data, and peripherals. Understanding the Cortex-M4 memory map is key to effectively utilizing the chip’s resources.
At its core, the Cortex-M4 memory consists of three main regions – Flash memory, SRAM, and Peripherals. The Flash stores code and constant data. SRAM provides memory for variable data used during execution. Peripherals include the various on-chip hardware blocks like timers, ADCs, GPIOs, etc. These regions can be flexibly mapped to different areas of the 4GB memory space.
The Flash memory stores the executable application code and constant data. It is non-volatile, meaning data is retained even when power is removed. The size of integrated Flash varies between MCUs, ranging from tens of KB to several MB.
Flash can be programmed via SWD/JTAG interfaces. Depending on the MCU, it may support read-while-write capability for firmware updates. Flash access time is relatively slower compared to SRAM. Code execution directly occurs from Flash.
In Cortex-M4, Flash is mapped to the bottom region of the memory map, starting at address 0x0000_0000. It can be configured to take up a contiguous block of up to 2GB in size. Typical configurations range from 128KB to 1MB.
SRAM provides volatile storage for variable data like stacks, heaps, globals, etc. It has high-speed access, making it ideal for data that needs frequent and fast reads/writes during code execution.
The Cortex-M4 integrates 8KB of embedded SRAM, but MCUs can add more external SRAM, ranging from ~10KB up to hundreds of KB. SRAM is mapped to higher memory regions, with addresses starting at 0x2000_0000. The exact base address and size can vary.
SRAM memory also contains the bit-band alias region which maps each bit in SRAM to a word-accessible bit band area. This allows atomic read-modify-write access to individual bits.
The Cortex-M4 incorporates various peripherals like GPIO, timers, ADC, DMA, etc. Each peripheral has a set of control/configuration registers mapped to the memory space. This allows software to access the peripherals via simple load/store instructions.
The peripheral memory region starts at address 0x4000_0000 and can extend up to 0x5FFF_FFFF. The exact mapping of individual peripherals is flexible and can differ across MCUs.
Common peripherals include:
- System control block: Power, clock, resets
- GPIO: General Purpose I/O ports
- Timers: Arm SysTick, general purpose, watchdog timers
- Communication: I2C, SPI, UART, CAN, USB
- ADC: Analog to Digital Converters
- DMA: Direct Memory Access controllers
- Debug/Trace: SWD, ETB, DWT
The NVIC and CPU ID registers are also mapped to the peripheral region. Overall, flexible peripheral mapping is a key aspect of Cortex-M4’s design.
Private Peripheral Bus
The Private Peripheral Bus (PPB) provides a dedicated interface to map peripherals that need high-bandwidth or real-time access. This avoids contention with core/DMA accesses on the system bus.
The PPB address space lies from 0xE000_0000 to 0xE00F_FFFF. Up to 240 peripherals can be connected on the PPB, with up to 4GB of address space per peripheral.
Typical PPB peripherals include high-speed communication controllers like USB, Ethernet, as well as external memories. The PPB bridge provides asynchronous access, enabling background I/O transfers without stalling the CPU.
System Control Space
The System Control Space (SCS) registers provide configuration and control functions for the core CPU. This includes setting exception priorities, fault behavior, memory access attributes, etc.
The SCS is present in all Cortex-M processors and is mapped at addresses 0xE000_E000 to 0xE000_EFFF. It is further divided into multiple blocks:
- CPUID: CPU identification (implementer, variant, architecture)
- Interrupt Controller (NVIC): Configures interrupts and exceptions
- SysTick: System timer and counter
- MPU: Memory Protection Unit
- FPU: Floating Point Unit
- Debug: Core debug/trace registers
The SCS is only accessible via the Cortex-M privilege mode, preventing user code from modifying protected system configurations.
While Flash and SRAM provide internal memory, Cortex-M4 MCUs can also support external memories like NOR/NAND Flash, SRAM, and SDRAM. These connect via buses like FSMC, QuadSPI, etc.
External memories can be flexibly mapped across the 4GB address space, letting software seamlessly access them as regular memory regions. Typical mappings are:
- NOR Flash: 0x6000_0000 to 0x7FFF_FFFF
- NAND Flash: 0x8000_0000 to 0x8FFF_FFFF
- SRAM: 0x9000_0000 to 0x9FFF_FFFF
- SDRAM: 0xA000_0000 to 0xDFFF_FFFF
Larger MCUs may provide MMU/MPU support to manage external memory access attributes and translations.
Code and Data Placement
Understanding the memory map is key to optimal placement of code, data, stacks, and heaps in Cortex-M4 applications. Some guidelines:
- Application code in internal Flash or external NOR Flash
- Constant data in Flash
- Global/static variables in SRAM
- Stacks/heaps in SRAM (grows down/up respectively)
- Framebuffers, FIFOs, etc in external SRAM
- Multimedia data (images, audio) in external SDRAM
On chip SRAM is limited, so care must be taken to not overflow stack/heap limits. The linker script defines region placements and sizes.
Memory Attribution Units
The Cortex-M4 includes a Memory Protection Unit (MPU) to control memory access permissions. This allows configuring access attributes for different memory regions.
Each MPU region is defined by:
- Base address
- Size (pow-of-2, min 32 bytes)
- Permissions: Privileged/User, Read/Write
- Memory type: Strongly Ordered, Device, Normal, etc.
Up to 16 MPU regions can be configured, supporting nested region definitions. This enables complex memory schemes tailored for different applications.
Memory Map Summary
In summary, the ARM Cortex-M4 provides a flexible memory architecture consisting of Flash, SRAM, and Peripheral regions. External memories can also be added for large data storage.
Understanding and properly utilizing the memory layout is key to building efficient applications. Optimized code/data placement, utilization of fast SRAM/SDRAM, and configuring MPU memory regions are some ways software can take advantage of the Cortex-M4 memory system.
This provides a high-level overview of the key memory regions – different MCUs can vary in exact mappings. Always refer to the chip’s reference manual for specific details. The flexible Cortex-M4 architecture enables developers to scale memory resources based on application requirements.