The Cortex-M0 is the smallest and most energy-efficient processor in the Cortex-M series of ARM processors. As an ultra low power microcontroller, the Cortex-M0 is designed for resource constrained devices and applications where cost and power consumption are critical factors. One of the ways the Cortex-M0 achieves its low power consumption is by having a very small on-chip memory footprint. The Cortex-M0 has only 16KB – 32KB of embedded SRAM on-chip. For many applications, this small on-chip memory is insufficient and external off-chip memory needs to be added. Integrating external memory with the Cortex-M0 does take some careful planning and configuration to ensure correct operation.
Types of External Memory
There are several common types of off-chip memory that can be interfaced with a Cortex-M0 microcontroller:
- SRAM – Static RAM provides fast access times for code execution and data storage. SRAM does not need refreshing like DRAM and is easy to interface with a microcontroller. However, SRAM is more expensive per bit than other memory types.
- PSRAM – Pseudo SRAM provides SRAM-like interface but is based on DRAM memory cells so it has higher density and lower cost. Refreshing needs to be handled transparently.
- DRAM – Dynamic RAM provides the highest density option for external memory. But DRAM is more complex to interface due to required refresh cycles and lower performance for random accesses.
- Flash – Flash memory provides non-volatile storage for data and code. NOR Flash allows execution in place (XIP) for code storage. NAND Flash requires buffering for code execution but provides higher densities for data storage.
- EEPROM – Electrically Erasable Programmable Read-Only Memory provides persistent storage that can be erased and reprogrammed electrically. Access times are slower than RAM but EEPROM allows non-volatile data storage.
For most Cortex-M0 designs, SRAM or PSRAM provides the best performance for off-chip memory due to the simple interface and fast access times. Flash memory is also commonly added for non-volatile program and data storage.
The Cortex-M0 microcontroller can interface with external memory through several peripheral interfaces:
- External Bus Interface (EBI) – The EBI allows connecting parallel external memories like SRAM, PSRAM, NOR Flash, etc. The EBI provides access to the memory on a cycle-by-cycle basis.
- Async Memory Interface – Asynchronous memories like SPI Flash, SPI SRAM, and I2C EEPROM can be connected via the Async interface. These lower speed devices don’t require a full parallel bus.
- FSMC – Some Cortex-M0 MCUs include a Flexible Static Memory Controller for interfacing synchronous memories like SRAM, PSRAM, and NOR Flash via a parallel bus with chip select signals.
The External Bus Interface (EBI) peripheral is the most common way to connect parallel SRAM or Flash devices. The EBI handles all the address latching, data multiplexing and handshaking required to interface asynchronous parallel memory devices. The EBI presents a simple SRAM-like interface to the Cortex-M0 core, hiding the complexity of the external memory device timings.
External Bus Interface Configuration
To connect an external memory device to the EBI, the interface needs to be configured correctly for the memory’s timing parameters and bus width. This is done via the EBI setup registers in the Cortex-M0 peripheral registers. The memory timing parameters are usually provided in the datasheet for the memory device. Some key parameters for the EBI configuration are:
- Memory type – SRAM, PSRAM, NOR Flash
- Memory bus width – 8-bit, 16-bit
- Read cycle timing – Address setup, address hold, read access time
- Write cycle timing – Address setup, address hold, write pulse width
- Idle cycles – cycles between reads and writes
The EBI controller handles all the handshaking with the external memory based on the configured timing parameters. This allows the Cortex-M0 core to access the external memory using simple bus read and write cycles.
Enabling Code Execution from External Memory
For many applications, the Cortex-M0 needs to execute code stored in external memory like NOR Flash. This requires configuring the Cortex-M0 Memory Protection Unit (MPU) correctly to allow instruction fetches from external memory regions. A couple key steps are required:
- Setup MPU regions – The MPU must be configured with a memory region that covers the external memory address range and is marked as executable.
- Set up vector table offset register – The VTOR register points to the interrupt vector table and must be configured to point to the vector table located in external memory.
With the MPU regions set up correctly and the VTOR pointing to the external vector table, the Cortex-M0 will start code execution from the defined reset handler location in external NOR Flash memory after reset.
Alternatives to EBI for External Memory Interface
While the External Bus Interface is the standard way to connect parallel external memories, some Cortex-M0 microcontrollers do not include an EBI peripheral. On these MCUs, external memory has to be interfaced via alternative peripherals like:
- FSMC – The Flexible Static Memory Controller provides comparable external parallel memory interfacing capability like the EBI, with configurable banks and chip selects.
- Async Memory Interface – SPI, QSPI and I2C interfaces can be used to connect slower asynchronous serial memories. These have lower performance than parallel memories.
- Bit-banging – General purpose I/O pins can be software driven to implement the handshake signaling of an external parallel memory interface. This is complex and lower performance.
When selecting a Cortex-M0 microcontroller, the availability of an EBI peripheral is an important consideration if external parallel memory needs to be used. However, in some low-cost applications an asynchronous serial memory interface like SPI or I2C can be sufficient despite lower performance.
Interfacing SRAM with EBI
Interfacing an external SRAM memory device to the EBI involves selecting the appropriate SRAM chip for the application’s memory requirements, wiring up the address/data bus connections between the SRAM and microcontroller device pins, and then configuring the EBI timing characteristics for the memory chip via the setup registers. A typical SRAM integration process would include:
- Select SRAM capacity needed, bus width (8/16 bit), and operating speed grade.
- Wire up address bus, data bus, and control signals (chip select, write enable, output enable) between SRAM and EBI pins.
- Look up read/write timing parameters for SRAM memory in datasheet.
- Configure EBI timing registers with SRAM parameters – read/write cycles, idle cycles, etc.
- Write test program to verify successful SRAM access via EBI.
- Modify chip select logic if required to match actual SRAM connections.
Properly interfacing the SRAM ensures the Cortex-M0 software can reliably read and write data to the external SRAM to expand its memory capacity. The EBI handshakes with the SRAM device using the configured timing parameters to access the memory in the background.
Interfacing NOR Flash Memory via EBI
NOR Flash memory provides non-volatile storage for both code and data. Interfacing parallel NOR Flash with the EBI is similar to SRAM – the memory is connected to the address/data bus and appropriate timing configurations are made. Some additional considerations for NOR Flash include:
- Enable/Disable chip select signal based on read/write operation
- Assert write enable signal during Flash write operation
- Configure MPU to allow code execution from Flash address range
- Set VTOR to point to vector table located in Flash memory
With the MPU and VTOR configured correctly, the Cortex-M0 will start executing code directly out of the NOR Flash after reset. The EBI handles all the NOR Flash access cycles in the background – fetch cycles for code reads, and erase/program cycles for writes to the Flash memory.
DMA Transfers for External Memory
Accessing external memory via the EBI interface involves the Cortex-M0 core reading and writing each byte or word one-by-one. This is inefficient for large data transfers. DMA (Direct Memory Access) provides a means to transfer large blocks of data to/from external memory without involvement from the Cortex-M0 core.
The steps for performing DMA transfers between internal SRAM and external memory are:
- Set up source (internal SRAM) and destination (external memory) addresses for DMA transfer.
- Configure DMA channel priority and transfer size.
- Trigger DMA transfer start – often via a software call or DMA request signal.
- DMA controller handles full block transfer in the background.
- Software polls for DMA complete interrupt flag.
Properly configured, DMA transfers allow the Cortex-M0 processor to move large chunks of data to/from external memory while continuing to execute application code, improving overall system performance.
Caching External Memory Accesses
Accessing external memory via the EBI is slower than internal SRAM access due to the associated bus delays. Cache memory can help improve the performance of external memory accesses. The Cortex-M0 does not contain internal cache, but some MCUs provide a system cache that can be used to cache external memory regions. When enabled, the system cache stores recent external memory accesses and provides faster access times for cached data.
To leverage system cache for external memory accesses:
- Configure cache size, line size, and memory regions to cache
- Enable system cache inalways on or enable-on-first-access mode
- Initialize cache upon startup
- Invalidate cache as needed when external memory content changes
Properly configured, cache memory improves average access times to slower external memories. The tradeoff is increased memory footprint and complexity for cache management.
Interfacing PSRAM Memory
PSRAM (Pseudo SRAM) provides a low cost DRAM memory solution with an SRAM-like interface. PSRAM can be connected to the Cortex-M0 EBI similar to asynchronous SRAM. However, refresh management logic needs to be implemented to periodically refresh the PSRAM memory cells.
Typical steps for integrating PSRAM with EBI:
- Connect PSRAM address/data bus to EBI.
- Configure EBI timing parameters for PSRAM.
- Implement periodic refresh logic using timers or hardware logic.
- Refresh handling can be done via dedicated PSRAM controller peripheral if present.
- Minimize external bus access during PSRAM refresh cycles.
With proper refresh handling, PSRAM provides a low cost, high density external RAM option for Cortex-M0. One tradeoff is suspended bus access during refresh cycles.
Interfacing External EEPROM via I2C
For non-volatile data storage and small programs, an I2C EEPROM provides a serial interface option. Typical steps to integrate an I2C EEPROM with Cortex-M0:
- Connect EEPROM to I2C peripheral pins.
- Configure I2C master interface for desired speed.
- Implement I2C protocol handling via interrupts or DMA.
- Develop software drivers to perform EEPROM read/write operations.
- Manage EEPROM addressing within full device capacity.
I2C EEPROM provides slower access times than parallel RAM, but allows serial interconnection without demanding bus timing requirements of parallel external memories.
Interfacing QSPI Flash Memory
QSPI (Queued SPI) Flash memory provides very high speed serial NOR Flash with performance rivaling parallel NOR Flash. A 4-line QSPI bus can support clock rates over 80MHz for external code execution and data storage. Key steps for QSPI integration:
- Connect QSPI Flash chip select, clock, and 4 data lines to MCU QSPI peripheral pins.
- Configure QSPI clock phase and polarity modes to match Flash device.
- Set up QSPI for memory-mapped addressing.
- Enable QSPI memory-mapped mode for Flash access.
- Configure MPU and VTOR to enable code execution from QSPI Flash.
The QSPI peripheral handles all protocol-level access details of the QSPI Flash device, allowing firmware to access external Flash via simple memory read/write bus cycles for maximum performance.
While the Cortex-M0 has limited embedded memory, its flexible external memory interfaces like EBI, FSMC, QSPI, and I2C allow integrating various off-chip memories for code and data expansion. Proper configuration to match the timing needs of the external memory device is key for reliable operation. Features like DMA transfers, system cache, and executing code from external NOR Flash enable high performance memory subsystems to overcome the limited on-chip memory of Cortex-M0 MCUs.