The Cortex-M3 is a 32-bit microcontroller developed by ARM Holdings. It features a von Neumann architecture with separate instruction and data buses along with advanced features like Thumb-2 instruction set, nested vectored interrupt controller, and optional memory protection unit.
Memory Architecture
The Cortex-M3 has a modified Harvard architecture, which means it has separate instruction and data memories but they are connected via the Memory Accelerator Module (MAM) which allows instructions to be fetched from data memory. This enables better code density compared to pure Harvard architecture.
The memory architecture consists of:
- Flash memory for storing code and constants
- RAM for storing data and stack
- Memory mapped peripherals
The Cortex-M3 supports up to 4GB of flash and up to 1GB of RAM. The flash and RAM can be on-chip or external or a combination of both. On-chip flash typically ranges from 32KB to 512KB while on-chip RAM ranges from 4KB to 128KB.
The following memory regions are present in the Cortex-M3 memory map:
- Code Region: Stores code and constants. Maps to internal or external flash.
- SRAM Region: Stores data and stack. Maps to internal SRAM.
- Peripheral Region: Memory mapped registers for peripherals like timers, GPIO, etc.
- Device Region: Additional peripherals including system control blocks.
The MAM module connects the instruction and data buses allowing access to code stored in SRAM for better flexibility.
Bus Architecture
The Cortex-M3 uses the Advanced Microcontroller Bus Architecture (AMBA) which defines the interfaces required for on-chip communication between various modules and peripherals. It consists of three main buses:
- Advanced High-performance Bus (AHB): The main system bus that connects the CPU, memory and high-speed peripherals. This is the backbone bus with high bandwidth.
- Advanced Peripheral Bus (APB): The peripheral bus that connects peripherals requiring lower bandwidth like UART, I2C, SPI etc. This bus runs at half the speed of AHB bus.
- Advanced Extensible Interface (AXI): An optional bus that provides high speed interface to external memory and peripherals.
The Cortex-M3 implements AMBA AHB-Lite protocol which is a subset of the full AHB protocol. It provides features like burst transfers, split transactions and single cycle bus master handover.
The memory accelerator module connects the instruction and data AHB interfaces. Additional ports are provided for tightly coupled memories like ITCM and DTCM Instruction and data tightly coupled memories help improve performance and determinism.
The system bus matrix connects the processor and other bus masters like DMA to the peripherals and memories via the AHB-Lite bus. It allows concurrent access paths to the peripherals with arbiters to handle contention.
AHB Lite Bus Features
- 32-bit system bus supporting up to 256 bus masters
- Burst transfers for improved efficiency
- Single cycle bus master handover for low latency
- Non-tristate implementation allowing concurrent bus master operation
- Configurable address decode allowing flexible memory mapping
- Peripheral DMA requests to offload data transfers from CPU
APB Bus Features
- 32-bit peripheral bus clocked at half rate of AHB bus
- Supports up to 16 peripheral bus masters
- Simpler interface compared to AHB suitable for low bandwidth peripherals
- Allows concurrent access to peripherals via separate read and write buses
Harvard vs Von Neumann Architecture
The Cortex-M3 uses a modified Harvard architecture which provides some benefits over pure Von Neumann architecture:
- Separation of instruction and data buses increases bandwidth
- No contention between instruction fetch and data access
- Instruction and data can be scaled independently based on need
- MAM module provides flexibility of Von Neumann architecture
Some limitations of Harvard architecture are code flexibility and higher memory cost. The MAM module helps overcome this by connecting instruction and data buses.
Thumb Instructions
The Cortex-M3 uses Thumb-2 instruction set which builds on top of the compact 16-bit Thumb instruction set used in earlier microcontrollers. The key features of Thumb-2 are:
- Mix of 16-bit and 32-bit instructions for improved code density
- 16-bit Thumb instruction set enhanced with additional instructions
- 32-bit instructions for better performance on loops, functions, etc.
- symmetrical 32-bit instruction encoding for simpler decoding
- Low interrupt latency of only 10 cycles
The Thumb-2 instruction set provides 60% better code density compared to earlier ARM architectures while improving performance by 40% making it ideal for embedded applications.
Nested Vectored Interrupt Controller
The Cortex-M3 incorporates a nested vectored interrupt controller (NVIC) which provides low latency interrupt handling using a priority based preemption model. Key features are:
- Supports up to 256 external and internal interrupt sources
- Configurable priorities for each interrupt
- Interrupt nesting with late arrival handling
- Wakeup interrupt controller for low power operation
- Reduces interrupt latency to as low as 10 cycles
The NVIC allows ultra low interrupt latency enabling real-time response in interrupt driven systems.
Memory Protection Unit
The optional memory protection unit (MPU) provides memory access control and hard fault exceptions generation for Cortex-M3 devices. The key features are:
- Up to 8 memory regions can be defined with individual permission controls
- Region sizes can be configured from 32 bytes to full memory size
- Programmable background region for default access permissions
- Permission attributes include read, write and execute
- Enables privileged software execution mode for OS-based designs
The MPU improves reliability and security by protecting memory areas from unintended access.
Cortex-M3 Configuration Options
The Cortex-M3 provides various configuration options to enable customization for specific application requirements:
- Memory Options: ITCM, DTCM, and MPU can be enabled based on need.
- Peripheral Bus: AHB or AMBA AXI bus can be selected.
- Debug Options: Debug access port and trace port options.
- Co-processor Interface: For connecting application specific co-processors.
- Number of Interrupts: Up to 256 external interrupts.
- CPU Clock Speed: Up to 200 MHz system clock speed.
These options allow tailoring the Cortex-M3 for diverse applications including industrial, automotive, consumer devices, etc.
Conclusion
In summary, the Cortex-M3 provides a high performance 32-bit processor architecture optimized for embedded applications. The modified Harvard architecture, Thumb-2 instruction set, AMBA AHB-Lite bus, NVIC, and MPU provide an excellent combination of performance, power efficiency, and ease of integration. The extensive configuration options make the Cortex-M3 a versatile solution that can be scaled across a wide range of embedded products.
